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| CY7C67200 EZ-OTGTM Programmable USB On-The-Go EZ-OTG Features * Single-chip programmable USB dual-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) and two USB ports * Supports USB OTG protocol * On-chip 48-MHz 16-bit processor with dynamically switchable clock speed * Configurable IO block supports a variety of IO options or up to 25 bits of General Purpose IO (GPIO) * 4K x 16 internal mask ROM contains built-in BIOS that supports a communication-ready state with access to I2CTM EEPROM interface, external ROM, UART, or USB * 8K x 16 internal RAM for code and data buffering * 16-bit parallel host port interface (HPI) with DMA/Mailbox data path for an external processor to directly access all on-chip memory and control on-chip SIEs * Fast serial port supports from 9600 baud to 2.0M baud * * * * SPI supports both master and slave Supports 12 MHz external crystal or clock 2.7V to 3.6V power supply voltage Package option: 48-pin FBGA Typical Applications EZ-OTG is a very powerful and flexible dual-role USB controller that supports a wide variety of applications. It is primarily intended to enable USB OTG capability in applications such as: * Cellular phones * PDAs and pocket PCs * Video and digital still cameras * MP3 players * Mass storage devices Block Diagram CY7C67200 CY7C67200 Control Timer 0 Timer 1 nRESET Watchdog UART I/F Vbus, ID OTG D+,DUSB-A I2C EEPROM I/F HOST/ Peripheral USB Ports SIE1 HSS I/F SHARED INPUT/OUTPUT PINS CY16 16-bit RISC CORE GPIO [24:0] SPI I/F D+,DUSB-A SIE2 4Kx16 ROM BIOS 8Kx16 RAM HPI I/F X1 X2 PLL Mobile Power Booster GPIO Cypress Semiconductor Corporation Document #: 38-08014 Rev. *G * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised November 14, 2006 [+] Feedback CY7C67200 Introduction EZ-OTGTM (CY7C67200) is Cypress Semiconductor's first USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-OTG has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode. EZ-OTG also has a programmable IO interface block allowing a wide range of interface options. Interrupts EZ-OTG provides 128 interrupt vectors. The first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts. General Timers and Watchdog Timer EZ-OTG has two built-in programmable timers and a watchdog timer. All three timers can generate an interrupt to the EZ-OTG. Power Management EZ-OTG has one main power-saving mode, Sleep. Sleep mode pauses all operations and provides the lowest power state. Processor Core Functional Overview An overview of the processor core components are presented in this section. Processor EZ-OTG has a general purpose 16-bit embedded RISC processor that runs at 48 MHz. Clocking EZ-OTG requires a 12 MHz source for clocking. Either an external crystal or TTL-level oscillator may be used. EZ-OTG has an internal PLL that produces a 48 MHz internal clock from the 12 MHz source. Memory EZ-OTG has a built-in 4K x 16 masked ROM and an 8K x 16 internal RAM. The masked ROM contains the EZ-OTG BIOS. The internal RAM can be used for program code or data. Table 1. Interface Options for GPIO Pins GPIO Pins GPIO31 GPIO30 GPIO29 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 HPI HSS SPI Interface Descriptions EZ-OTG has a variety of interface options for connectivity, with several interface options available. See Table 1 to understand how the interfaces share pins and can coexist. Below are some general guidelines: * I2C EEPROM and OTG do not conflict with any interfaces * HPI is mutually exclusive to HSS, SPI, and UART UART I2C SCL/SDA SCL/SDA OTG OTGID INT nRD nWR nCS A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CTS RTS RXD TXD MOSI SCK nSSI MISO TX RX Document #: 38-08014 Rev. *G Page 2 of 78 [+] Feedback CY7C67200 USB Interface EZ-OTG has two built-in Host/Peripheral SIEs that each have a single USB transceiver, meeting the USB 2.0 specification requirements for full and low speed (high speed is not supported). In Host mode, EZ-OTG supports two downstream ports; each supports control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-OTG supports one peripheral port with eight endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support Interrupt, bulk (up to 64 bytes per packet), or isochronous transfers (up to 1023 bytes per packet size). EZ-OTG also supports a combination of Host and Peripheral ports simultaneously, as shown in Table 2. Table 2. USB Port Configuration Options Port Configurations OTG OTG + 1 Host OTG + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 2 Hosts 1 Host 1 Host 2 Peripherals 1 Peripheral 1 Peripheral Port 1A OTG OTG OTG Host Peripheral Host Host - Peripheral Peripheral - Port 2A - Host Peripheral Peripheral Host Host - Host Peripheral - Peripheral OTG Interface EZ-OTG has one USB port that is compatible with the USB On-The-Go supplement to the USB 2.0 specification. The USB OTG port has various hardware features to support Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). OTG is only supported on USB PORT 1A. OTG Features * Internal Charge Pump to supply and control VBUS * VBUS Valid Status (above 4.4V) * VBUS Status for 2.4V < VBUS < 0.8V * ID Pin Status * Switchable 2-Kohm internal discharge resistor on VBUS * Switchable 500-ohm internal pull-up resistor on VBUS * Individually switchable internal pull-up and pull-down resistors on the USB data lines OTG Pins Table 4. OTG Interface Pins Pin Name DM1A DP1A OTGVBUS OTGID CSwitchA CSwitchB General Purpose IO Interface Pin Number F2 E3 C1 F4 D1 D2 USB Features * USB 2.0 compatible for full and low speed * Up to two downstream USB host ports * Up to two upstream USB peripheral ports * Configurable endpoint buffers (pointer and length), must reside in internal RAM * Up to eight available peripheral endpoints (1 control endpoint) * Supports Control, Interrupt, Bulk, and Isochronous transfers * Internal DMA channels for each endpoint * Internal pull up and pull down resistors * Internal Series termination resistors on USB data lines USB Pins Table 3. USB Interface Pins Pin Name DM1A DP1A DM2A DP2A Pin Number F2 E3 C2 D3 EZ-OTG has up to 25 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overall number of available GPIOs. GPIO Description All Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48 MHz clock cycles. GPIO pins are latched directly into registers, a single flip-flop. Unused Pin Descriptions Unused USB pins must be tri-stated with the D+ line pulled high through the internal pull-up resistor and the D- line pulled low through the internal pull-down resistor. Unused GPIO pins must be configured as outputs and driven low. UART Interface EZ-OTG has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as a development port or for other interface requirements. The UART interface is exposed through GPIO pins. Document #: 38-08014 Rev. *G Page 3 of 78 [+] Feedback CY7C67200 UART Features * Supports baud rates of 900 to 115.2K * 8-N-1 UART Pins Table 5. UART Interface Pins Pin Name TX RX I2C EEPROM Interface EZ-OTG provides a master-only I2C interface for external serial EEPROMs. The serial EEPROM can be used to store application-specific code and data. This I2C interface is only to be used for loading code out of EEPROM, it is not a general I2C interface. The I2C EEPROM interface is a BIOS implementation and is exposed through GPIO pins. Refer to the BIOS documentation for additional details on this interface. I2C EEPROM Features * Supports EEPROMs up to 64 KB (512K bit) * Auto-detection of EEPROM size I2C EEPROM Pins Table 6. I2C EEPROM Interface Pins Pin Name SCK SDA LARGE EEPROM SCK SDA Serial Peripheral Interface EZ-OTG provides an SPI interface for added connectivity. EZ-OTG may be configured as either an SPI master or SPI slave. The SPI interface can be exposed through GPIO pins or the External Memory port. SPI Features * Master or slave mode operation * DMA block transfer and PIO byte transfer modes * Full duplex or half duplex data communication * 8-byte receive FIFO and 8-byte transmit FIFO * Selectable master SPI clock rates from 250 kHz to 12 MHz * Selectable master SPI clock phase and polarity * Slave SPI signaling synchronization and filtering * Slave SPI clock rates up to 2 MHz * Maskable interrupts for block and byte transfer modes F3 H3 Pin Number SMALL EEPROM H3 F3 Pin Number B5 B4 * Individual bit transfer for non-byte aligned serial communication in PIO mode * Programmable delay timing for the active/inactive master SPI clock * Auto or manual control for master mode slave select signal * Complete access to internal memory SPI Pins The SPI port has a few different pin location options as shown in Table 7. The pin location is selectable via the GPIO Control register [0xC006]. Table 7. SPI Interface Pins Pin Name nSSI SCK MOSI MISO High-Speed Serial Interface EZ-OTG provides an HSS interface. The HSS interface is a programmable serial connection with baud rate from 9600 baud to 2M baud. The HSS interface supports both byte and block mode operations as well as hardware and software handshaking. Complete control of EZ-OTG can be accomplished through this interface via an extensible API and communication protocol. The HSS interface can be exposed through GPIO pins or the External Memory port. HSS Features * 8-bit, no parity code * Programmable baud rate from 9600 baud to 2M baud * Selectable 1- or 2-stop bit on transmit * Programmable intercharacter gap timing for Block Transmit * 8-byte receive FIFO * Glitch filter on receive * Block mode transfer directly to/from EZ-OTG internal memory (DMA transfer) * Selectable CTS/RTS hardware signal handshake protocol * Selectable XON/XOFF software handshake protocol * Programmable Receive interrupt, Block Transfer Done interrupts * Complete access to internal memory HSS Pins Table 8. HSS Interface Pins Pin Name CTS RTS RX TX Pin Number F6 E4 E5 E6 Pin Number F6 or C6 D5 D4 C5 Document #: 38-08014 Rev. *G Page 4 of 78 [+] Feedback CY7C67200 Host Port Interface (HPI) EZ-OTG has an HPI interface. The HPI interface provides DMA access to the EZ-OTG internal memory by an external host, plus a bidirectional mailbox register for supporting high-level communication protocols. This port is designed to be the primary high-speed connection to a host processor. Complete control of EZ-OTG can be accomplished through this interface via an extensible API and communication protocol. Other than the hardware communication protocols, a host processor has identical control over EZ-Host whether connecting to the HPI or HSS port. The HPI interface is exposed through GPIO pins. Note It should be noted that for up to 3 ms after BIOS starts executing, GPIO[24:19] and GPIO[15:8] will be driven as outputs for a test mode. If these pins need to be used as inputs, a series resistor is required (10 ohm to 48 ohm is recommended). Refer to BIOS documentation for addition details. See section "Reset Pin" on page 9. HPI Features * 16-bit data bus interface * 16 MB/s throughput * Auto-increment of address pointer for fast block mode transfers * Direct memory access (DMA) to internal memory * Bidirectional Mailbox register * Byte Swapping * Complete access to internal memory * Complete control of SIEs through HPI * Dedicated HPI Status register HPI Pins Table 9. HPI Interface Pins [1, 2] Table 9. HPI Interface Pins [1, 2] (continued) Pin Name D7 D6 D5 D4 D3 D2 D1 D0 Pin Number B5 B4 C4 B3 A3 C3 A2 B2 The two HPI address pins are used to address one of four possible HPI port registers as shown in Table 10 below. Table 10.HPI Addressing HPI A[1:0] HPI Data HPI Mailbox HPI Address HPI Status Charge Pump Interface VBUS for the USB On-The-Go (OTG) port can be produced by EZ-OTG using its built-in charge pump and some external components. The circuit connections should look similar to Figure 1 below. Figure 1. Charge Pump D1 CSWITCHA A1 0 0 1 1 A0 0 1 0 1 D2 Pin Name INT nRD nWR nCS A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 Pin Number H4 G4 H5 G5 H6 F5 F6 E4 E5 E6 D4 D5 C6 C5 CY7C67200 CSWITCHB C1 OTGVBUS VBUS C2 Component details: * D1 and D2: Schottky diodes with a current rating greater than 60 mA. * C1: Ceramic capacitor with a capacitance of 0.1 F. * C2: Capacitor value must be no more that 6.5 F since that is the maximum capacitance allowed by the USB OTG specification for a dual-role device. The minimum value of C2 is 1 F. There are no restrictions on the type of capacitor for C2. If the VBUS charge pump circuit is not to be used, CSWITCHA, CSWITCHB, and OTGVBUS can be left unconnected. Notes 1. HPI_INT is for the Outgoing Mailbox Interrupt. 2. HPI strobes are negative logic sampled on rising edge. Document #: 38-08014 Rev. *G Page 5 of 78 [+] Feedback CY7C67200 Charge Pump Features * Meets OTG Supplement Requirements, see Table 41, "DC Characteristics: Charge Pump," on page 66. Charge Pump Pins Table 11.Charge Pump Interface Pins Pin Name OTGVBUS CSwitchA CSwitchB Booster Interface EZ-OTG has an on-chip power booster circuit for use with power supplies that range between 2.7V and 3.6V. The booster circuit boosts the power to 3.3V nominal to supply power for the entire chip. The booster circuit requires an external inductor, diode, and capacitor. During power down mode, the circuit is disabled to save power. Figure 2 shows how to connect the booster circuit. Figure 2. Power Supply Connection With Booster Pin Number C1 D1 D2 Figure 3. Power Supply Connection Without Booster BOOSTVcc 3.0V to 3.6V Power Supply VSWITCH VCC AVCC Booster Pins Table 12.Charge Pump Interface Pins Pin Name BOOSTVcc VSWITCH Pin Number F1 E2 BOOSTVcc L1 2.7V to 3.6V Power Supply Crystal Interface The recommended crystal circuit to be used with EZ-OTG is shown in Figure 4. If an oscillator is used instead of a crystal circuit, connect it to XTALIN and leave XTALOUT unconnected. For further information on the crystal requirements, see Table 39, "Crystal Requirements," on page 65. Figure 4. Crystal Interface VSWITCH D1 3.3V VCC AVCC C1 XTALIN Component details: * L1: Inductor with inductance of 10 H and a current rating of at least 250 mA * D1: Schottky diode with a current rating of at least 250 mA * C1: Tantalum or ceramic capacitor with a capacitance of at least 2.2 F Figure 3 shows how to connect the power supply when the booster circuit is not being used. CY7C67200 Y1 XTALOUT C1 = 22 pF 12MHz Parallel Resonant Fundamental Mode 500uW 20-33pf 5% C2 = 22 pF Document #: 38-08014 Rev. *G Page 6 of 78 [+] Feedback CY7C67200 Crystal Pins Table 13.Crystal Pins Pin Name XTALIN XTALOUT Boot Configuration Interface EZ-OTG can boot into any one of four modes. The mode it boots into is determined by the TTL voltage level of GPIO[31:30] at the time nRESET is deasserted. Table 14 shows the different boot pin combinations possible. After a reset pin event occurs, the BIOS bootup procedure executes for up to 3 ms. GPIO[31:30] are sampled by the BIOS during bootup only. After bootup these pins are available to the application as GPIOs. Table 14.Boot Configuration Interface GPIO31 (Pin 39) 0 0 1 1 GPIO30 (Pin 40) 0 1 0 1 Boot Mode Host Port Interface (HPI) High Speed Serial (HSS) Serial Peripheral Interface (SPI, slave mode) I2C EEPROM (Standalone Mode) Pin Number G3 G2 Operational Modes There are two modes of operation: Coprocessor and Standalone. Coprocessor Mode EZ-OTG can act as a coprocessor to an external host processor. In this mode, an external host processor drives EZ-OTG and is the main processor rather then EZ-OTG's own 16-bit internal CPU. An external host processor may interface to EZ-OTG through one of the following three interfaces in coprocessor mode: * HPI mode, a 16-bit parallel interface with up to 16 MBytes transfer rate * HSS mode, a serial interface with up to 2M baud transfer rate * SPI mode, a serial interface with up to 2 Mbits/s transfer rate. At bootup GPIO[31:30] determine which of these three interfaces are used for coprocessor mode. Refer to Table 14 for details. Bootloading begins from the selected interface after POR + 3 ms of BIOS bootup. Standalone Mode In standalone mode, there is no external processor connected to EZ-OTG. Instead, EZ-OTG's own internal 16-bit CPU is the main processor and firmware is typically downloaded from an EEPROM. Optionally, firmware may also be downloaded via USB. Refer to Table 14 for booting into standalone mode. After booting into standalone mode (GPIO[31:30] = `11'), the following pins are affected: * GPIO[31:30] are configured as output pins to examine the EEPROM contents. * GPIO[28:27] are enabled for debug UART mode. * GPIO[29] is configured as OTGID for OTG applications on PORT1A. -- If OTGID is logic 1 then PORT1A (OTG) is configured as a USB peripheral. -- If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host. * Ports 1B, 2A, and 2B default as USB peripheral ports. * All other pins remain INPUT pins. GPIO[31:30] must be pulled high or low, as needed, using resistors tied to VCC or GND with resistor values between 5K ohm and 15K ohm. GPIO[31:30] must not be tied directly to VCC or GND. Note that in Standalone mode, the pull ups on those two pins are used for the serial I2C EEPROM (if implemented). The resistors used for these pull ups must conform to the serial EEPROM manufacturer's requirements. If any mode other then standalone is chosen, EZ-OTG will be in coprocessor mode. The device will power up with the appropriate communication interface enabled according to its boot pins and wait idle until a coprocessor communicates with it. See the BIOS documentation for greater detail on the boot process. Document #: 38-08014 Rev. *G Page 7 of 78 [+] Feedback CY7C67200 Minimum Hardware Requirements for Standalone Mode - Peripheral Only Figure 5. Minimum Standalone Hardware Configuration - Peripheral Only EZ-OTG CY7C67200 VReg VBus D+ DGND SHIELD Bootstrap Options Vcc Vcc 10k 10k GPIO[30] GPIO[31] SCL* SDA* Int. 16k x8 Code / Data VCC A0 A1 A2 GND Up to 64k x8 EEPROM VCC WP SCL SDA GND, AGND, BoostGND *Bootloading begins after POR + 3ms BIOS bootup *GPIO[31:30] Up to 2k x8 >2k x8 to 64k x8 31 30 SCL SDA SDA SCL Reserved XIN 12MHz 22pf VCC, AVCC, BoostVCC DPlus DMinus nRESET Reset Logic Standard-B or Mini-B Bootloading Firmware XOUT 22pf * Parallel Resonant Fundamental Mode 500uW 20-33pf 5% Power Savings and Reset Description The EZ-OTG modes and reset conditions are described in this section. Power Savings Mode Description EZ-OTG has one main power savings mode, Sleep. For detailed information on Sleep mode; See section "Sleep". Sleep mode is used for USB applications to support USB suspend and non USB applications as the main chip power down mode. In addition, EZ-OTG is capable of slowing down the CPU clock speed through the CPU Speed register [0xC008] without affecting other peripheral timing. Reducing the CPU clock speed from 48 MHz to 24 MHz reduces the overall current draw by around 8 mA while reducing it from 48 MHz to 3 MHz reduces the overall current draw by approximately 15 mA. Sleep Sleep mode is the main chip power down mode and is also used for USB suspend. Sleep mode is entered by setting the Sleep Enable (bit 1) of the Power Control register [0xC00A]. During Sleep mode (USB Suspend) the following events and states are true: * GPIO pins maintain their configuration during sleep (in suspend). * External Memory Address pins are driven low. * XTALOUT is turned off. * Internal PLL is turned off. * Firmware must disable the charge pump (OTG Control register [0xC098]) causing OTGVBUS to drop below 0.2V. Otherwise OTGVBUS will only drop to VCC - (2 schottky diode drops). * Booster circuit is turned off. * USB transceivers is turned off. * CPU suspends until a programmable wakeup event. Document #: 38-08014 Rev. *G Page 8 of 78 [+] Feedback CY7C67200 External (Remote) Wakeup Source There are several possible events available to wake EZ-OTG from Sleep mode as shown in Table 15. These may also be used as remote wakeup options for USB applications. See section "Power Control Register [0xC00A] [R/W]" on page 13. Upon wakeup, code begins executing within 200 ms, the time it takes the PLL to stabilize. Table 15.wakeup Sources[3, 4] Wakeup Source (if enabled) USB Resume OTGVBUS OTGID HPI HSS SPI IRQ0 (GPIO 24) Level Any Edge Read Read Read Any Edge Event D+/D- Signaling registers, USB control registers, the stack, and other BIOS variables. The upper internal memory space contains EZ-OTG control registers from 0xC000 to 0xC0FF and the BIOS ROM itself from 0xE000 to 0xFFFF. For more information on the reserved lower memory or the BIOS ROM, refer to the Programmers documentation and the BIOS documentation. During development with the EZ-OTG toolset, the lower area of User's space (0x04A4 to 0x1000) should be left available to load the GDB stub. The GDB stub is required to allow the toolset debug access into EZ-OTG. Figure 6. Memory Map Internal Memory HW INTs 0x0000 - 0x00FF SW INTs 0x0100 - 0x011F 0x0120 - 0x013F 0x0140 - 0x0148 0x014A - 0x01FF 0x0200- 0x02FF 0x0300- 0x030F 0x0310- 0x03FF 0x0400- 0x04A2 0x04A4- 0x3FFF Primary Registers Swap Registers HPI Int / Mailbox LCP Variables USB Registers Slave Setup Packet BIOS Stack USB Slave & OTG USER SPACE ~15K Power-On Reset (POR) Description The length of the power-on-reset event can be defined by (VCC ramp to valid) + (Crystal start up). A typical application might utilize a 12-ms power-on-reset event = ~7 ms + ~5 ms, respectively. Reset Pin The Reset pin is active low and requires a minimum pulse duration of sixteen 12-MHz clock cycles (1.3 ms). A reset event restores all registers to their default POR settings. Code execution then begins 200 ms later at 0xFF00 with an immediate jump to 0xE000, the start of BIOS. Note It should be noted that for up to 3 ms after BIOS starts executing, GPIO[24:19] and GPIO[15:8] will be driven as outputs for a test mode. If these pins need to be used as inputs, a series resistor is required (10 ohm to 48 ohm is recommended). Refer to BIOS documentation for addition details. USB Reset A USB Reset affects registers 0xC090 and 0xC0B0, all other registers remain unchanged. Memory Map Memory map information is presented in this section. Mapping The EZ-OTG has just over 24 KB of addressable memory mapped from 0x0000 to 0xFFFF. This 24 KB contains both program and data space and is byte addressable. Figure 6. shows the various memory region address locations. Internal Memory Of the internal memory, 15 KB is allocated for user's program and data code. The lower memory space from 0x0000 to 0x04A2 is reserved for interrupt vectors, general purpose Notes 3. Read data will be discarded (dummy data). 4. HPI_INT will assert on a USB Resume.registers 0xC000- 0xC0FF Control Registers 0xE000- 0xFFFF BIOS Document #: 38-08014 Rev. *G Page 9 of 78 [+] Feedback CY7C67200 Registers Some registers have different functions for a read vs. a write access or USB host vs. USB device mode. Therefore, registers of this type have multiple definitions for the same address. The default register values listed in this data sheet may be altered to some other value during BIOS initialization. Refer to the BIOS documentation for Register initialization information. Processor Control Registers There are eight registers dedicated to general processor control. Each of these registers is covered in this section and is summarized in Table 16. Table 16.Processor Control Registers Register Name CPU Flags Register Register Bank Register Hardware Revision Register CPU Speed Register Power Control Register Interrupt Enable Register Breakpoint Register USB Diagnostic Register Address 0xC000 0xC002 0xC004 0xC008 0xC00A 0xC00E 0xC014 0xC03C R/W R R/W R R/W R/W R/W R/W W CPU Flags Register [0xC000] [R] Figure 7. CPU Flags Register Bit # Field Read/Write Default Bit # 0 7 0 6 ...Reserved Field Read/Write Default 0 0 0 0 5 0 4 Global Interrupt Enable R X 15 14 13 12 Reserved... 0 3 Negative Flag R X 0 2 Overflow Flag R X 0 1 Carry Flag R X 0 0 Zero Flag R X 11 10 9 8 Register Description The CPU Flags register is a read only register that gives processor flags status. Global Interrupt Enable (Bit 4) The Global Interrupt Enable bit indicates if the Global Interrupts are enabled. 1: Enabled 0: Disabled Negative Flag (Bit 3) The Negative Flag bit indicates if an arithmetic operation results in a negative answer. 1: MS result bit is `1' 0: MS result bit is not `1' Overflow Flag (Bit 2) The Overflow Flag bit indicates if an overflow condition has occurred. An overflow condition can occur if an arithmetic result was either larger than the destination operand size (for addition) or smaller than the destination operand should allow for subtraction. 1: Overflow occurred 0: Overflow did not occur Carry Flag (Bit 1) The Carry Flag bit indicates if an arithmetic operation resulted in a carry for addition, or borrow for subtraction. 1: Carry/Borrow occurred 0: Carry/Borrow did not occur Zero Flag (Bit 0) The Zero Flag bit indicates if an instruction execution resulted in a `0'. 1: Zero occurred 0: Zero did not occur Document #: 38-08014 Rev. *G Page 10 of 78 [+] Feedback CY7C67200 Bank Register [0xC002] [R/W] Figure 8. Bank Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 7 R/W 0 6 ...Address R/W 0 R/W 0 X . 15 14 13 R/W 0 5 12 Address... R/W 0 4 11 R/W 0 3 X 10 R/W 0 2 Reserved X 9 R/W 0 1 X 8 R/W 1 0 X Register Description The Bank register maps registers R0-R15 into RAM. The eleven MSBs of this register are used as a base address for registers R0-R15. A register address is automatically generated by: 1. Shifting the four LSBs of the register address left by 1 2. ORing the four shifted bits of the register address with the 12 MSBs of the Bank Register 3. Forcing the LSB to zero For example, if the Bank register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 will be read. See Table 17 for details. Table 17.Bank Register Example Register Hex Value Bank 0x0100 R14 0x000E << 1 = 0x001C RAM 0x011C Location Address (Bits [15:4]) The Address field is used as a base address for all register addresses to start from. Reserved All reserved bits must be written as `0'. Binary Value 0000 0001 0000 0000 0000 0000 0001 1100 0000 0001 0001 1100 Hardware Revision Register [0xC004] [R] Figure 9. Revision Register Bit # Field Read/Write Default Bit # Field Read/Write Default R X R X R X R X R X 7 R X 6 R X 5 R X 4 ...Revision R X R X R X R X 15 14 13 12 Revision... R X 3 R X 2 R X 1 R X 0 11 10 9 8 Register Description The Hardware Revision register is a read-only register that indicates the silicon revision number. The first silicon revision is represented by 0x0101. This number is increased by one for each new silicon revision. Revision (Bits [15:0]) The Revision field contains the silicon revision number. Document #: 38-08014 Rev. *G Page 11 of 78 [+] Feedback CY7C67200 CPU Speed Register [0xC008] [R/W] Figure 10. CPU Speed Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 7 0 6 ...Reserved 0 0 R/W 1 1 0 5 0 4 15 14 13 12 Reserved... 0 3 0 2 CPU Speed R/W R/W 1 R/W 1 0 1 0 0 11 10 9 8 Register Description The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU; all other peripheral timing is still based on the 48-MHz system clock (unless otherwise noted). CPU Speed (Bits[3:0]) The CPU Speed field is a divisor that selects the operating speed of the processor as defined in Table 18. Table 18.CPU Speed Definition CPU Speed [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved All reserved bits must be written as `0'. Processor Speed 48 MHz/1 48 MHz/2 48 MHz/3 48 MHz/4 48 MHz/5 48 MHz/6 48 MHz/7 48 MHz/8 48 MHz/9 48 MHz/10 48 MHz/11 48 MHz/12 48 MHz/13 48 MHz/14 48 MHz/15 48 MHz/16 Document #: 38-08014 Rev. *G Page 12 of 78 [+] Feedback CY7C67200 Power Control Register [0xC00A] [R/W] Figure 11. Power Control Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 7 HPI Wake Enable R/W 0 0 15 Reserved 14 Host/Device 2 Wake Enable R/W 0 6 Reserved 0 13 Reserved 0 5 12 11 10 Reserved 0 2 Boost 3V OK R 0 9 HSS Wake Enable R/W 0 1 Sleep Enable R/W 0 8 SPI Wake Enable R/W 0 0 Halt Enable R/W 0 Host/Device 1 OTG Wake Enable Wake Enable R/W 0 4 GPI Wake Enable R/W 0 R/W 0 3 Reserved 0 Register Description The Power Control register controls the power-down and wakeup options. Either the sleep mode or the halt mode options can be selected. All other writable bits in this register can be used as a wakeup source while in sleep mode. Host/Device 2 Wake Enable (Bit 14) The Host/Device 2 Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 2 transition. This wake up from the SIE port does not cause an interrupt to the on-chip CPU. 1: Enable wakeup on Host/Device 2 transition. 0: Disable wakeup on Host/Device 2 transition. Host/Device 1 Wake Enable (Bit 12) The Host/Device 1 Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 1 transition. This wakeup from the SIE port does not cause an interrupt to the on-chip CPU. 1: Enable wakeup on Host/Device 1 transition 0: Disable wakeup on Host/Device 1 transition OTG Wake Enable (Bit 11) The OTG Wake Enable bit enables or disables a wakeup condition to occur on either an OTG VBUS_Valid or OTG ID transition (IRQ20). 1: Enable wakeup on OTG VBUS valid or OTG ID transition 0: Disable wakeup on OTG VBUS valid or OTG ID transition HSS Wake Enable (Bit 9) The HSS Wake Enable bit enables or disables a wakeup condition to occur on an HSS Rx serial input transition. The processor may take several hundreds of microseconds before being operational after wakeup. Therefore, the incoming data byte that causes the wakeup will be discarded. 1: Enable wakeup on HSS Rx serial input transition 0: Disable wakeup on HSS Rx serial input transition SPI Wake Enable (Bit 8) The SPI Wake Enable bit enables or disables a wakeup condition to occur on a falling SPI_nSS input transition. The processor may take several hundreds of microseconds before being operational after wakeup. Therefore, the incoming data byte that causes the wakeup will be discarded. 1: Enable wakeup on falling SPI nSS input transition 0: Disable SPI_nSS interrupt HPI Wake Enable (Bit 7) The HPI Wake Enable bit enables or disables a wakeup condition to occur on an HPI interface read. 1: Enable wakeup on HPI interface read 0: Disable wakeup on HPI interface read GPI Wake Enable (Bit 4) The GPI Wake Enable bit enables or disables a wakeup condition to occur on a GPIO(25:24) transition. 1: Enable wakeup on GPIO(25:24) transition 0: Disable wakeup on GPIO(25:24) transition Boost 3V OK (Bit 2) The Boost 3V OK bit is a read only bit that returns the status of the OTG Boost circuit. 1: Boost circuit not ok and internal voltage rails are below 3.0V 0: Boost circuit ok and internal voltage rails are at or above 3.0V Sleep Enable (Bit 1) Setting this bit to `1' immediately initiates SLEEP mode. While in SLEEP mode, the entire chip is paused achieving the lowest standby power state. All operations are paused, the internal clock is stopped, the booster circuit and OTG VBUS charge pump are all powered down, and the USB transceivers are powered down. All counters and timers are paused but will retain their values. SLEEP mode exits by any activity selected in this register. When SLEEP mode ends, instruction execution resumes within 0.5 ms. 1: Enable Sleep Mode 0: No Function Document #: 38-08014 Rev. *G Page 13 of 78 [+] Feedback CY7C67200 Halt Enable (Bit 0) Setting this bit to `1' immediately initiates HALT mode. While in HALT mode, only the CPU is stopped. The internal clock still runs and all peripherals still operate, including the USB engines. The power savings using HALT in most cases will be minimal, but in applications that are very CPU intensive the incremental savings may provide some benefit. The HALT state is exited when any enabled interrupt is triggered. Upon exiting the HALT state, one or two instructions Interrupt Enable Register [0xC00E] [R/W] immediately following the HALT instruction may be executed before the waking interrupt is serviced (you may want to follow the HALT instruction with two NOPs). 1: Enable Halt Mode 0: No Function Reserved All reserved bits must be written as `0'. Figure 12. Interrupt Enable Register Bit # 15 14 Reserved Field Read/Write Default Bit # 0 7 HSS Interrupt Enable R/W 0 0 6 In Mailbox Interrupt Enable R/W 0 0 5 Out Mailbox Interrupt Enable R/W 0 13 12 OTG Interrupt Enable R/W 0 4 Reserved 11 SPI Interrupt Enable R/W 0 3 UART Interrupt Enable R/W 0 10 Reserved 9 8 Host/Device 2 Host/Device 1 Interrupt Interrupt Enable Enable R/W 0 1 Timer 1 Interrupt Enable R/W 0 R/W 0 0 Timer 0 Interrupt Enable R/W 0 0 2 GPIO Interrupt Enable R/W 0 Field Read/Write Default 1 Register Description The Interrupt Enable Register allows control of the hardware interrupt vectors. OTG Interrupt Enable (Bit 12) The OTG Interrupt Enable bit enables or disables the OTG ID/OTG4.4V Valid hardware interrupt. 1: Enable OTG interrupt 0: Disable OTG interrupt SPI Interrupt Enable (Bit 11) The SPI Interrupt Enable bit enables or disables the following three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA Block Done. 1: Enable SPI interrupt 0: Disable SPI interrupt Host/Device 2 Interrupt Enable (Bit 9) The Host/Device 2 Interrupt Enable bit enables or disables all of the following Host/Device 2 hardware interrupts: Host 2 USB Done, Host 2 USB SOF/EOP, Host 2 WakeUp/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB, Device 2 Endpoint n. 1: Enable Host 2 and Device 2 interrupt 0: Disable Host 2 and Device 2 interrupt Host/Device 1 Interrupt Enable (Bit 8) The Host/Device 1 Interrupt Enable bit enables or disables all of the following Host/Device 1 hardware interrupts: Host 1 USB Done, Host 1 USB SOF/EOP, Host 1 WakeUp/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device 1 Endpoint n. 1: Enable Host 1 and Device 1 interrupt 0: Disable Host 1 and Device 1 interrupt HSS Interrupt Enable (Bit 7) The HSS Interrupt Enable bit enables or disables the following High-speed Serial Interface hardware interrupts: HSS Block Done, and HSS RX Full. 1: Enable HSS interrupt 0: Disable HSS interrupt In Mailbox Interrupt Enable (Bit 6) The In Mailbox Interrupt Enable bit enables or disables the HPI: Incoming Mailbox hardware interrupt. 1: Enable MBXI interrupt 0: Disable MBXI interrupt Out Mailbox Interrupt Enable (Bit 5) The Out Mailbox Interrupt Enable bit enables or disables the HPI: Outgoing Mailbox hardware interrupt. 1: Enable MBXO interrupt 0: Disable MBXO interrupt Document #: 38-08014 Rev. *G Page 14 of 78 [+] Feedback CY7C67200 UART Interrupt Enable (Bit 3) The UART Interrupt Enable bit enables or disables the following UART hardware interrupts: UART TX and UART RX. 1: Enable UART interrupt 0: Disable UART interrupt GPIO Interrupt Enable (Bit 2) The GPIO Interrupt Enable bit enables or disables the General Purpose IO Pins Interrupt (See the GPIO Control Register). When GPIO bit is reset, all pending GPIO interrupts are also cleared. 1: Enable GPIO interrupt 0: Disable GPIO interrupt Timer 1 Interrupt Enable (Bit 1) The Timer 1 Interrupt Enable bit enables or disables the TImer1 Interrupt Enable. When this bit is reset, all pending Timer 1 interrupts are cleared. 1: Enable TM1 interrupt 0: Disable TM1 interrupt Timer 0 Interrupt Enable (Bit 0) The Timer 0 Interrupt Enable bit enables or disables the TImer0 Interrupt Enable. When this bit is reset, all pending Timer 0 interrupts are cleared. 1: Enable TM0 interrupt 0: Disable TM0 interrupt Reserved All reserved bits must be written as `0'. Breakpoint Register [0xC014] [R/W] Figure 13. Breakpoint Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8 Register Description The Breakpoint Register holds the breakpoint address. When the program counter match this address, the INT127 interrupt occurs. To clear this interrupt, a zero value must be written to this register. Address (Bits [15:0]) The Address field is a 16-bit field containing the breakpoint address. Document #: 38-08014 Rev. *G Page 15 of 78 [+] Feedback CY7C67200 USB Diagnostic Register [0xC03C] [R/W] Figure 14. USB Diagnostic Register Bit # 15 Reserved Field Read/Write Default Bit # Field Read/Write Default 0 0 7 ...Reserved 14 Port 2A Diagnostic Enable R/W 0 6 Pull-down Enable R/W 0 13 Reserved 12 Port 1A Diagnostic Enable R/W 0 4 FS Pull-up Enable R/W 0 0 3 Reserved 0 R/W 0 0 2 11 10 Reserved... 9 8 0 5 LS Pull-up Enable R/W 0 0 1 Force Select R/W 0 0 0 R/W 0 Register Description The USB Diagnostic Register provides control of diagnostic modes. It is intended for use by device characterization tests, not for normal operations. This register is Read/Write by the on-chip CPU but is write-only via the HPI port. Port 2A Diagnostic Enable (Bit 15) The Port 2A Diagnostic Enable bit enables or disables Port 2A for the test conditions selected in this register. 1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD 0: Do not apply test conditions Port 1A Diagnostic Enable (Bit 15) The Port 1A Diagnostic Enable bit enables or disables Port 1A for the test conditions selected in this register. 1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD 0: Do not apply test conditions Pull-down Enable (Bit 6) The Pull-down Enable bit enables or disables full-speed pull-down resistors (pull down on both D+ and D-) for testing. 1: Enable pull-down resistors on both D+ and D- 0: Disable pull-down resistors on both D+ and D- LS Pull-up Enable (Bit 5) The LS Pull-up Enable bit enables or disables a low-speed pull-up resistor (pull up on D-) for testing. 1: Enable low-speed pull-up resistor on D- 0: Pull-up resistor is not connected on D- FS Pull-up Enable (Bit 4) The FS Pull-up Enable bit enables or disables a full-speed pull-up resistor (pull up on D+) for testing. 1: Enable full-speed pull-up resistor on D+ 0: Pull-up resistor is not connected on D+ Force Select (Bits [2:0]) The Force Select field bit selects several different test condition states on the data lines (D+/D-). See Table 19 for details. Table 19.Force Select Definition Force Select [2:0] 1xx 01x 001 000 Reserved All reserved bits must be written as `0'. Timer Registers There are three registers dedicated to timer operations. Each of these registers are discussed in this section and are summarized in Table 20. Table 20.Timer Registers Register Name Watchdog Timer Register Timer 0 Register Timer 1 Register Address 0xC00C 0xC010 0xC012 R/W R/W R/W R/W Data Line State Assert SE0 Toggle JK Assert J Assert K Document #: 38-08014 Rev. *G Page 16 of 78 [+] Feedback CY7C67200 Watchdog Timer Register [0xC00C] [R/W] Figure 15. Watchdog Timer Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 7 ...Reserved R/W 0 6 R/W 0 5 Timeout Flag R/W 0 R/W 0 0 4 Period Select R/W 0 15 14 13 12 Reserved... R/W R/W 0 3 R/W 0 2 Lock Enable R/W 0 R/W 0 1 WDT Enable R/W 0 R/W 0 0 Reset Strobe W 0 11 10 9 8 Register Description The Watchdog Timer register provides status and control over the Watchdog timer. The Watchdog timer can also interrupt the processor. Timeout Flag (Bit 5) The Timeout Flag bit indicates if the Watchdog timer has expired. The processor can read this bit after exiting a reset to determine if a Watchdog timeout occurred. This bit is cleared on the next external hardware reset. 1: Watchdog timer expired 0: Watchdog timer did not expire Period Select (Bits [4:3]) The Period Select field is defined in Table 21. If this time expires before the Reset Strobe bit is set, the internal processor is reset. Table 21.Period Select Definition Period Select[4:3] 00 01 10 11 WDT Period Value 1.4 ms 5.5 ms 22.0 ms 66.0 ms Lock Enable (Bit 2) The Lock Enable bit does not allow any writes to this register until a reset. In doing so the Watchdog timer can be set up and enabled permanently so that it can only be cleared on reset (the WDT Enable bit is ignored). 1: Watchdog timer permanently set 0: Watchdog timer not permanently set WDT Enable (Bit 1) The WDT Enable bit enables or disables the Watchdog timer. 1: Enable Watchdog timer operation 0: Disable Watchdog timer operation Reset Strobe (Bit 0) The Reset Strobe is a write-only bit that resets the Watchdog timer count. It must be set to `1' before the count expires to avoid a Watchdog trigger 1: Reset Count Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 17 of 78 [+] Feedback CY7C67200 Timer n Register [R/W] * Timer 0 Register 0xC010 * Timer 1 Register 0xC012 Figure 16. Timer n Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 ...Count R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 Count... R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 11 10 9 8 Register Description The Timer n Register sets the Timer n count. Both Timer 0 and Timer 1 decrement by one every 1-s clock tick. Each can provide an interrupt to the CPU when the timer reaches zero. Count (Bits [15:0]) The Count field sets the Timer count. General USB Registers There is one set of registers dedicated to general USB control. This set consists of two identical registers, one for Host/Device Port 1 and one for Host/Device Port 2. This register set has functions for both USB host and USB peripheral options and is covered in this section and summarized in Table 22. USB Host-only registers are covered in Section "USB Host Only Registers" on page 19 and USB Device-only registers are covered in Section "USB Device Only Registers" on page 28. Table 22.USB Registers Register Name USB n Control Register USB n Control Register [R/W] * USB 1 Control Register 0xC08A * USB 2 Control Register 0xC0AA Figure 17. USB n Control Register Bit # Field Read/Write Default Bit # Field Read/Write Default X 7 Port A Resistors Enable R/W 0 0 X 6 Reserved 0 15 Reserved 14 13 Port A D+ Status R X 5 12 Port A D- Status R X 4 11 Reserved 0 3 10 LOA R/W 0 2 Suspend Enable R/W 0 1 Reserved 0 9 Mode Select R/W 0 0 Port A SOF/EOP Enable R/W 0 8 Reserved 0 Address (SIE1/SIE2) 0xC08A/0xC0AA R/W R/W Port A Force D State R/W 0 R/W 0 Register Description The USB n Control register is used in both host and device mode. It monitors and controls the SIE and the data lines of the USB ports. This register can be accessed by the HPI interface. Document #: 38-08014 Rev. *G Page 18 of 78 [+] Feedback CY7C67200 Port A D+ Status (Bit 13) The Port A D+ Status bit is a read-only bit that indicates the value of DATA+ on Port A. 1: D+ is high 0: D+ is low Port A D- Status (Bit 12) The Port A D- Status bit is a read-only bit that indicates the value of DATA- on Port A. 1: D- is high 0: D- is low LOA (Bit 10) The LOA bit selects the speed of Port A. 1: Port A is set to Low-speed mode 0: Port A is set to Full-speed mode Mode Select (Bit 9) The Mode Select bit sets the SIE for host or device operation. When set for device operation only one USB port is supported. The active port is selected by the Port Select bit in the Host n Count Register. 1: Host mode 0: Device mode Port A Resistors Enable (Bit 7) The Port A Resistors Enable bit enables or disables the pull-up/pull-down resistors on Port A. When enabled, the Mode Select bit and LOA bit of this register sets the pull-up/pull-down resistors appropriately. When the Mode Select is set for Host mode, the pull-down resistors on the data lines (D+ and D-) are enabled. When the Mode Select is set for Device mode, a single pull-up resistor on either D+ or D-, determined by the LOA bit, will be enabled. See Table 23 for details. 1: Enable pull-up/pull-down resistors 0: Disable pull-up/pull-down resistors Table 23.USB Data Line Pull-up and Pull-down Resistors L0A X X 1 0 Mode Select X 1 0 0 Port n Resistors Enable 0 1 1 1 Function Pull up/Pull down on D+ and D- Disabled Pull down on D+ and D- Enabled Pull up on USB D- Enabled Pull up on USB D+ Enabled Table 24.Port A Force D State Port A Force D State MSB LSB 0 0 0 1 1 0 1 1 Suspend Enable (Bit 2) The Suspend Enable bit enables or disables the suspend feature on both ports. When suspend is enabled the USB transceivers are powered down and can not transmit or received USB packets but can still monitor for a wakeup condition. 1: Enable suspend 0: Disable suspend Port A SOF/EOP Enable (Bit 0) The Port A SOF/EOP Enable bit is only applicable in host mode. In Device mode this bit must be written as `0'. In host mode this bit enables or disables SOFs or EOPs for Port A. Either SOFs or EOPs will be generated depending on the LOA bit in the USB n Control Register when Port A is active. 1: Enable SOFs or EOPs 0: Disable SOFs or EOPs Reserved All reserved bits must be written as `0'. USB Host Only Registers There are twelve sets of dedicated registers to USB host only operation. Each set consists of two identical registers (unless otherwise noted); one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized in Table 25. Table 25.USB Host Only Register Register Name Host n Control Register Host n Address Register Host n Count Register Host n Endpoint Status Register Host n PID Register Host n Count Result Register Host n Device Address Register Host n Interrupt Enable Register Host n Status Register Host n SOF/EOP Count Register Host n SOF/EOP Counter Register Host n Frame Register Address (Host 1/Host 2) 0xC080/0xC0A0 0xC082/0xC0A2 0xC084/0xC0A4 0xC086/0xC0A6 0xC086/0xC0A6 0xC088/0xC0A8 0xC088/0xC0A8 0xC08C/0xC0AC 0xC090/0xC0B0 0xC092/0xC0B2 0xC094/0xC0B4 0xC096/0xC0B6 R/W R/W R/W R/W R W R W R/W R/W R/W R R Function Normal Operation Force USB Reset, SE0 State Force J-State Force K-State Port A Force D State (Bits [4:3]) The Port A Force D State field controls the forcing state of the D+ D- data lines for Port A. This field forces the state of the Port A data lines independent of the Port Select bit setting. See Table 24 for details. Document #: 38-08014 Rev. *G Page 19 of 78 [+] Feedback CY7C67200 Host n Control Register [R/W] * Host 1 Control Register 0xC080 * Host 2 Control Register 0xC0A0 Figure 18. Host n Control Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 7 Preamble Enable R/W 0 0 6 Sequence Select R/W 0 0 5 Sync Enable R/W 0 0 4 ISO Enable R/W 0 0 15 14 13 12 Reserved 0 3 0 2 Reserved 0 0 0 1 0 0 Arm Enable R/W 0 11 10 9 8 Register Description The Host n Control register allows high-level USB transaction control. Preamble Enable (Bit 7) The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. This bit should only be set when communicating with a low-speed device. 1: Enable Preamble packet 0: Disable Preamble packet Sequence Select (Bit 6) The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receiving data packets; sequence checking must be handled in firmware. 1: Send DATA1 0: Send DATA0 Sync Enable (Bit 5) The Sync Enable bit synchronizes the transfer with the SOF packet in full-speed mode and the EOP packet in low-speed mode. 1: The next enabled packet will be transferred after the SOF or EOP packet is transmitted 0: The next enabled packet will be transferred as soon as the SIE is free ISO Enable (Bit 4) The ISO Enable bit enables or disables an Isochronous transaction. 1: Enable Isochronous transaction 0: Disable Isochronous transaction Arm Enable (Bit 0) The Arm Enable bit arms an endpoint and starts a transaction. This bit is automatically cleared to `0' when a transaction is complete. 1: Arm endpoint and begin transaction 0: Endpoint disarmed Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 20 of 78 [+] Feedback CY7C67200 Host n Address Register [R/W] * Host 1 Address Register 0xC082 * Host 2 Address Register 0xC0A2 Figure 19. Host n Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8 Register Description The Host n Address register is used as the base pointer into memory space for the current host transactions. Address (Bits [15:0]) The Address field sets the address pointer into internal RAM or ROM. Host n Count Register [R/W] * Host 1 Count Register 0xC084 * Host 2 Count Register 0xC0A4 Figure 20. Host n Count Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 15 14 13 Reserved 0 4 ...Count R/W 0 R/W 0 R/W 0 R/W 0 0 3 0 2 R/W 0 1 12 11 10 9 Count... R/W 0 0 8 Register Description The Host n Count register is used to hold the number of bytes (packet length) for the current transaction. The maximum packet length is 1023 bytes in ISO mode. The Host Count value is used to determine how many bytes to transmit, or the maximum number of bytes to receive. If the number of received bytes is greater then the Host Count value then an overflow condition will be flagged by the Overflow bit in the Host n Endpoint Status register. Count (Bits [9:0]) The Count field sets the value for the current transaction data packet length. This value is retained when switching between host and device mode, and back again. Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 21 of 78 [+] Feedback CY7C67200 Host n Endpoint Status Register [R] * Host 1 Endpoint Status Register 0xC086 * Host 2 Endpoint Status Register 0xC0A6 Figure 21. Host n Endpoint Status Register Bit # Field Read/Write Default Bit # 0 7 Stall Flag Field Read/Write Default R 0 R 0 0 6 NAK Flag 0 5 Length Exception Flag R 0 0 4 Reserved 15 14 Reserved 13 12 11 Overflow Flag R 0 3 Sequence Status R 0 10 Underflow Flag R 0 2 Timeout Flag R 0 0 1 Error Flag R 0 9 Reserved 0 0 ACK Flag R 0 8 0 Register Description The Host n Endpoint Status register is a read-only register that provides status for the last USB transaction. Overflow Flag (Bit 11) The Overflow Flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the Host n Count Register. The Overflow Flag should be checked in response to a Length Exception signified by the Length Exception Flag set to `1'. 1: Overflow condition occurred 0: Overflow condition did not occur Underflow Flag (Bit 10) The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specified in the Host n Count register. The Underflow Flag should be checked in response to a Length Exception signified by the Length Exception Flag set to `1'. 1: Underflow condition occurred 0: Underflow condition did not occur Stall Flag (Bit 7) The Stall Flag bit indicates that the peripheral device replied with a Stall in the last transaction. 1: Device returned Stall 0: Device did not return Stall NAK Flag (Bit 6) The NAK Flag bit indicates that the peripheral device replied with a NAK in the last transaction. 1: Device returned NAK 0: Device did not return NAK Length Exception Flag (Bit 5) The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximum Host Count specified in the Host n Count register. A Length Exception can either mean an overflow or underflow and the Overflow and Underflow flags (bits 11 and 10, respectively) should be checked to determine which event occurred. 1: An overflow or underflow condition occurred 0: An overflow or underflow condition did not occur Sequence Status (Bit 3) The Sequence Status bit indicates the state of the last received data toggle from the device. Firmware is responsible for monitoring and handling the sequence status. The Sequence bit is only valid if the ACK bit is set to `1'. The Sequence bit is set to `0' when an error is detected in the transaction and the Error bit will be set. 1: DATA1 0: DATA0 Timeout Flag (Bit 2) The Timeout Flag bit indicates if a timeout condition occurred for the last transaction. A timeout condition can occur when a device either takes too long to respond to a USB host request or takes too long to respond with a handshake. 1: Timeout occurred 0: Timeout did not occur Error Flag (Bit 1) The Error Flag bit indicates a transaction failed for any reason other than the following: Timeout, receiving a NAK, or receiving a STALL. Overflow and Underflow are not considered errors and do not affect this bit. CRC5 and CRC16 errors will result in an Error flag along with receiving incorrect packet types. 1: Error detected 0: No error detected Document #: 38-08014 Rev. *G Page 22 of 78 [+] Feedback CY7C67200 ACK Flag (Bit 0) The ACK Flag bit indicates two different conditions depending on the transfer type. For non-Isochronous transfers, this bit represents a transaction ending by receiving or sending an ACK packet. For Isochronous transfers, this bit represents a successful transaction that will not be represented by an ACK packet. 1: For non-Isochronous transfers, the transaction was ACKed. For Isochronous transfers, the transaction was completed successfully. 0: For non-Isochronous transfers, the transaction was not ACKed. For Isochronous transfers, the transaction was not completed successfully. Host n PID Register [W] * Host 1 PID Register 0xC086 * Host 2 PID Register 0xC0A6 Figure 22. Host n PID Register Bit # Field Read/Write Default Bit # Field Read/Write Default W 0 W 0 0 7 0 6 PID Select W 0 W 0 W 0 0 5 0 4 15 14 13 12 Reserved 0 3 0 2 W 0 0 1 W 0 0 0 W 0 11 10 9 8 Endpoint Select Register Description The Host n PID register is a write-only register that provides the PID and Endpoint information to the USB SIE to be used in the next transaction. PID Select (Bits [7:4]) The PID Select field defined as in Table 26. ACK and NAK tokens are automatically sent based on settings in the Host n Control register and do not need to be written in this register. Table 26.PID Select Definition PID TYPE set-up IN OUT SOF PID Select [7:4] 1101 (D Hex) 1001 (9 Hex) 0001 (1 Hex) 0101 (5 Hex) Table 26.PID Select Definition (continued) PID TYPE PREAMBLE NAK STALL DATA0 DATA1 Endpoint Select (Bits [3:0]) The Endpoint field allows addressing of up to 16 different endpoints. Reserved All reserved bits must be written as `0'. PID Select [7:4] 1100 (C Hex) 1010 (A Hex) 1110 (E Hex) 0011 (3 Hex) 1011 (B Hex) Document #: 38-08014 Rev. *G Page 23 of 78 [+] Feedback CY7C67200 Host n Count Result Register [R] * Host 1 Count Result Register 0xC088 * Host 2 Count Result Register 0xC0A8 Figure 23. Host n Count Result Register Bit # Field Read/Write Default Bit # Field Read/Write Default R 0 R 0 R 0 R 0 R 0 7 R 0 6 R 0 5 R 0 4 ...Result R 0 R 0 R 0 R 0 15 14 13 12 Result... R 0 3 R 0 2 R 0 1 R 0 0 11 10 9 8 Register Description The Host n Count Result register is a read-only register that contains the size difference in bytes between the Host Count Value specified in the Host n Count register and the last packet received. If an overflow or underflow condition occurs, that is the received packet length differs from the value specified in the Host n Count register, the Length Exception Flag bit in the Host n Endpoint Status register will be set. The value in this register is only valid when the Length Exception Flag bit is set and the Error Flag bit is not set; both bits are in the Host n Endpoint Status register. Result (Bits [15:0]) The Result field contains the differences in bytes between the received packet and the value specified in the Host n Count register. If an overflow condition occurs, Result [15:10] is set to `111111', a 2's complement value indicating the additional byte count of the received packet. If an underflow condition occurs, Result [15:0] indicates the excess byte count (number of bytes not used). Reserved All reserved bits must be written as `0'. Host n Device Address Register [W] * Host 1 Device Address Register 0xC088 * Host 2 Device Address Register 0xC0A8 Figure 24. Host n Device Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 7 ...Reserved 0 W 0 W 0 W 0 0 6 0 5 0 4 15 14 13 12 Reserved... 0 3 Address W 0 W 0 W 0 W 0 0 2 0 1 0 0 11 10 9 8 Register Description The Host n Device Address register is a write-only register that contains the USB Device Address that the host wishes to communicate with. Address (Bits [6:0]) The Address field contains the value of the USB address for the next device that the host is going to communicate with. This value must be written by firmware. Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 24 of 78 [+] Feedback CY7C67200 Host n Interrupt Enable Register [R/W] * Host 1 Interrupt Enable Register 0xC08C * Host 2 Interrupt Enable Register 0xC0AC Figure 25. Host n Interrupt Enable Register Bit # Field Read/Write Default Bit # 7 Reserved Field Read/Write Default 0 R/W 0 0 15 VBUS Interrupt Enable R/W 0 6 Port A Wake Interrupt Enable 14 ID Interrupt Enable R/W 0 0 5 Reserved 0 4 Port A Connect Change Interrupt Enable R/W 0 0 13 12 Reserved 0 3 0 2 Reserved 11 10 9 SOF/EOP Interrupt Enable R/W 0 1 0 Done Interrupt Enable 0 R/W 0 8 Reserved 0 0 Register Description The Host n Interrupt Enable register allows control over host-related interrupts. In this register a bit set to `1' enables the corresponding interrupt while `0' disables the interrupt. VBUS Interrupt Enable (Bit 15) The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled this interrupt triggers on both the rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2. 1: Enable VBUS interrupt 0: Disable VBUS interrupt ID Interrupt Enable (Bit 14) The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2. 1: Enable ID interrupt 0: Disable ID interrupt SOF/EOP Interrupt Enable (Bit 9) The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP timer interrupt. 1: Enable SOF/EOP timer interrupt 0: Disable SOF/EOP timer interrupt Port A Wake Interrupt Enable (Bit 6) The Port A Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port A. 1: Enable remote wakeup interrupt for Port A 0: Disable remote wakeup interrupt for Port A Port A Connect Change Interrupt Enable (Bit 4) The Port A Connect Change Interrupt Enable bit enables or disables the Connect Change interrupt on Port A. This interrupt triggers when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state). 1: Enable Connect Change interrupt 0: Disable Connect Change interrupt Done Interrupt Enable (Bit 0) The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt. The USB Transfer Done triggers when either the host responds with an ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout. This interrupt is used for both Port A and Port B. 1: Enable USB Transfer Done interrupt 0: Disable USB Transfer Done interrupt Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 25 of 78 [+] Feedback CY7C67200 Host n Status Register [R/W] * Host 1 Status Register 0xC090 * Host 2 Status Register 0xC0B0 Figure 26. Host n Status Register Bit # Field Read/Write Default Bit # 15 VBUS Interrupt Flag R/W X 7 Reserved Field Read/Write Default X 14 ID Interrupt Flag R/W X 6 Port A Wake Interrupt Flag R/W X X 5 Reserved X 4 Port A Connect Change Interrupt Flag R/W X 13 12 Reserved X 3 Reserved X 2 Port A SE0 Status R/W X 11 10 9 SOF/EOP Interrupt Flag R/W X 1 Reserved 8 Reserved X 0 Done Interrupt Flag R/W X X X X Register Description The Host n Status register provides status information for host operation. Pending interrupts can be cleared by writing a `1' to the corresponding bit. This register can be accessed by the HPI interface. VBUS Interrupt Flag (Bit 15) The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Host 1 and is a reserved bit in Host 2. 1: Interrupt triggered 0: Interrupt did not trigger ID Interrupt Flag (Bit 14) The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin. This bit is only available for Host 1 and is a reserved bit in Host 2. 1: Interrupt triggered 0: Interrupt did not trigger SOF/EOP Interrupt Flag (Bit 9) The SOF/EOP Interrupt Flag bit indicates the status of the SOF/EOP Timer interrupt. This bit triggers `1' when the SOF/EOP timer expires. 1: Interrupt triggered 0: Interrupt did not trigger Port A Wake Interrupt Flag (Bit 6) The Port A Wake Interrupt Flag bit indicates remote wakeup on Port A. 1: Interrupt triggered 0: Interrupt did not trigger Port A Connect Change Interrupt Flag (Bit 4) The Port A Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port A. This bit triggers `1' on either a rising edge or falling edge of a USB Reset condition (device inserted or removed). Together with the Port A SE0 Status bit, it can be determined whether a device was inserted or removed. 1: Interrupt triggered 0: Interrupt did not trigger Port A SE0 Status (Bit 2) The Port A SE0 Status bit indicates if Port A is in an SE0 state or not. Together with the Port A Connect change Interrupt Flag bit, it can be determined whether a device was inserted (non-SE0 condition) or removed (SE0 condition). 1: SE0 condition 0: Non-SE0 condition Done Interrupt Flag (Bit 0) The Done Interrupt Flag bit indicates the status of the USB Transfer Done interrupt. The USB Transfer Done triggers when either the host responds with an ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout. This interrupt is used for both Port A and Port B. 1: Interrupt triggered 0: Interrupt did not trigger Document #: 38-08014 Rev. *G Page 26 of 78 [+] Feedback CY7C67200 Host n SOF/EOP Count Register [R/W] * Host 1 SOF/EOP Count Register 0xC092 * Host 2 SOF/EOP Count Register 0xC0B2 Figure 27. Host n SOF/EOP Count Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 1 R/W 1 R/W 1 R/W 0 0 7 15 Reserved 0 6 R/W 1 5 R/W 0 4 ...Count R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 3 14 13 12 11 Count... R/W 1 2 R/W 1 1 R/W 0 0 10 9 8 Register Description The Host n SOF/EOP Count register contains the SOF/EOP Count Value that is loaded into the SOF/EOP counter. This value is loaded each time the SOF/EOP counter counts down to zero. The default value set in this register at power-up is 0x2EE0, which will generate a 1-ms time frame. The SOF/EOP counter is a down counter decremented at a 12-MHz rate. When this register is read, the value returned is the programmed SOF/EOP count value. Count (Bits [13:0]) The Count field sets the SOF/EOP counter duration. Reserved All reserved bits must be written as `0'. Host n SOF/EOP Counter Register [R] * Host 1 SOF/EOP Counter Register 0xC094 * Host 2 SOF/EOP Counter Register 0xC0B4 Figure 28. Host n SOF/EOP Counter Register Bit # Field Read/Write Default Bit # Field Read/Write Default R X R X R X R X X 7 15 Reserved X 6 R X 5 R X 4 ...Counter R X R X R X R X R X 3 14 13 12 11 Counter... R X 2 R X 1 R X 0 10 9 8 Register Description The Host n SOF/EOP Counter register contains the current value of the SOF/EOP down counter. This value can be used to determine the time remaining in the current frame. Counter (Bits [13:0]) The Counter field contains the current value of the SOF/EOP down counter. Document #: 38-08014 Rev. *G Page 27 of 78 [+] Feedback CY7C67200 Host n Frame Register [R] * Host 1 Frame Register 0xC096 * Host 2 Frame Register 0xC0B6 Figure 29. Host n Frame Register Bit # Field Read/Write Default Bit # Field Read/Write Default R 0 R 0 R 0 R 0 0 7 0 6 15 14 13 Reserved 0 5 0 4 ...Frame R 0 R 0 R 0 R 0 0 3 R 0 2 12 11 10 9 Frame... R 0 1 R 0 0 8 Register Description The Host n Frame register maintains the next frame number to be transmitted (current frame number + 1). This value is updated after each SOF transmission. This register resets to 0x0000 after each CPU write to the Host n SOF/EOP Count register (Host 1: 0xC092, Host 2: 0xC0B2). Frame (Bits [10:0]) The Frame field contains the next frame number to be transmitted. Table 27.USB Device Only Registers Register Name Device n Endpoint n Control Register Device n Endpoint n Address Register Device n Endpoint n Count Register Device n Endpoint n Status Register Device n Endpoint n Count Result Register Device n Interrupt Enable Register Device n Address Register Device n Status Register Device n Frame Number Register Device n SOF/EOP Count Register Reserved All reserved bits must be written as `0'. USB Device Only Registers There are ten sets of USB Device Only registers. All sets consist of at least two registers, one for Device Port 1 and one for Device Port 2. In addition, each Device port has eight possible endpoints. This gives each endpoint register set eight registers for each Device Port for a total of 16 registers per set. The USB Device Only registers are covered in this section and summarized in Table 27. Address (Device 1/Device 2) 0x02n0 0x02n2 0x02n4 0x02n6 0x02n8 0xC08C/0xC0AC 0xC08E/0xC0AE 0xC090/0xCB0 0xC092/0xC0B2 0xC094/0xC0B4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R W Device n Endpoint n Control Register [R/W] * Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280] * Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290] * Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0] * Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0] * Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0] * Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0] * Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0] * Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0] Document #: 38-08014 Rev. *G Page 28 of 78 [+] Feedback CY7C67200 Figure 30. Device n Endpoint n Control Register Bit # Field Read/Write Default Bit # X 7 IN/OUT Ignore Enable R/W X X 6 Sequence Select R/W X X 5 Stall Enable R/W X X 4 ISO Enable R/W X 15 14 13 12 Reserved X 3 NAK Interrupt Enable R/W X X 2 Direction Select R/W X X 1 Enable X 0 Arm Enable R/W X 11 10 9 8 Field Read/Write Default R/W X Register Description The Device n Endpoint n Control register provides control over a single EP in device mode. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Control register. IN/OUT Ignore Enable (Bit 6) The IN/OUT Ignore Enable bit forces endpoint 0 (EP0) to ignore all IN and OUT requests. This bit must be set so that EP0 only excepts Setup packets at the start of each transfer. This bit must be cleared to except IN/OUT transactions. This bit only applies to EP0. 1: Ignore IN/OUT requests 0: Do not ignore IN/OUT requests Sequence Select (Bit 6) The Sequence Select bit determines whether a DATA0 or a DATA1 will be sent for the next data toggle. This bit has no effect on receiving data packets, sequence checking must be handled in firmware. 1: Send a DATA1 0: Send a DATA0 Stall Enable (Bit 5) The Stall Enable bit sends a Stall in response to the next request (unless it is a setup request, which are always ACKed). This is a sticky bit and continues to respond with Stalls until cleared by firmware. 1: Send Stall 0: Do not send Stall ISO Enable (Bit 4) The ISO Enable bit enables and disables an Isochronous transaction. This bit is only valid for EPs 1-7 and has no function for EP0. 1: Enable Isochronous transaction 0: Disable Isochronous transaction NAK Interrupt Enable (Bit 3) The NAK Interrupt Enable bit enables and disables the generation of an Endpoint n interrupt when the device responds to the host with a NAK. The Endpoint n Interrupt Enable bit in the Device n Interrupt Enable register must also be set. When a NAK is sent to the host, the corresponding EP Interrupt Flag in the Device n Status register will be set. In addition, the NAK Flag in the Device n Endpoint n Status register will be set. 1: Enable NAK interrupt 0: Disable NAK interrupt Direction Select (Bit 2) The Direction Select bit needs to be set according to the expected direction of the next data stage in the next transaction. If the data stage direction is different from what is set in this bit, it will get NAKed and either the IN Exception Flag or the OUT Exception Flag will be set in the Device n Endpoint n Status register. If a setup packet is received and the Direction Select bit is set incorrectly, the setup will be ACKed and the Set-up Status Flag will be set (refer to the setup bit of the Device n Endpoint n Status register for details). 1: OUT transfer (host to device) 0: IN transfer (device to host) Enable (Bit 1) The Enable bit must be set to allow transfers to the endpoint. If Enable is set to `0' then all USB traffic to this endpoint is ignored. If Enable is set `1' and Arm Enable (bit 0) is set `0' then NAKs will automatically be returned from this endpoint (except setup packets, which are always ACKed as long as the Enable bit is set). 1: Enable transfers to an endpoint 0: Do not allow transfers to an endpoint Arm Enable (Bit 0) The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to `0' when a transaction is complete. 1: Arm endpoint 0: Endpoint disarmed Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 29 of 78 [+] Feedback CY7C67200 Device n Endpoint n Address Register [R/W] * Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282] * Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292] * Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2] * Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2] * Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2] * Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2] * Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2] * Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2] Figure 31. Device n Endpoint n Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W X R/W X R/W X R/W X R/W X 7 R/W X 6 R/W X 5 R/W X 4 ...Address R/W X R/W X R/W X R/W X 15 14 13 12 Address... R/W X 3 R/W X 2 R/W X 1 R/W X 0 11 10 9 8 Register Description The Device n Endpoint n Address register is used as the base pointer into memory space for the current Endpoint transaction. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Address register. Address (Bits [15:0]) The Address field sets the base address for the current transaction on a signal endpoint. Device n Endpoint n Count Register [R/W] * Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284] * Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294] * Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4] * Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4] * Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4] * Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4] * Device n Endpoint 6 Count Register [Device 1: 0x0264 Device 2: 0x02E4] * Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4] Figure 32. Device n Endpoint n Count Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W X R/W X R/W X R/W X X 7 X 6 X 5 15 14 13 Reserved X 4 ...Count R/W X R/W X R/W X R/W X X 3 X 2 R/W X 1 12 11 10 9 Count... R/W X 0 8 Document #: 38-08014 Rev. *G Page 30 of 78 [+] Feedback CY7C67200 Register Description The Device n Endpoint n Count register designates the maximum packet size that can be received from the host for OUT transfers for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN token for a single endpoint. The maximum packet length is 1023 bytes in ISO mode. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Count register. Count (Bits [9:0]) The Count field sets the current transaction packet length for a single endpoint. Reserved All reserved bits must be written as `0'. Device n Endpoint n Status Register [R/W] * Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286] * Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296] * Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6] * Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6] * Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6] * Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6] * Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6] * Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6] Figure 33. Device n Endpoint n Status Register Bit # Field Read/Write Default Bit # Field Read/Write Default X 7 Stall Flag R/W X X 6 NAK Flag R/W X X 5 Length Exception Flag R/W X X 4 Setup Flag R/W X 15 14 Reserved 13 12 11 Overflow Flag R/W X 3 Sequence Flag R/W X 10 Underflow Flag R/W X 2 Timeout Flag R/W X 9 OUT Exception Flag R/W X 1 Error Flag R/W X 8 IN Exception Flag R/W X 0 ACK Flag R/W X Register Description The Device n Endpoint n Status register provides packet status information for the last transaction received or transmitted. This register is updated in hardware and does not need to be cleared by firmware. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Status register. The Device n Endpoint n Status register is a memory-based register that must be initialized to 0x0000 before USB Device operations are initiated. After initialization, this register must not be written to again. Overflow Flag (Bit 11) The Overflow Flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the Device n Endpoint n Count register. The Overflow Flag should be checked in response to a Length Exception signified by the Length Exception Flag set to `1'. 1: Overflow condition occurred 0: Overflow condition did not occur Underflow Flag (Bit 10) The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specified in the Device n Endpoint n Count register. The Underflow Flag should be checked in response to a Length Exception signified by the Length Exception Flag set to `1'. 1: Underflow condition occurred 0: Underflow condition did not occur OUT Exception Flag (Bit 9) The OUT Exception Flag bit indicates when the device received an OUT packet when armed for an IN. 1: Received OUT when armed for IN 0: Received IN when armed for IN Document #: 38-08014 Rev. *G Page 31 of 78 [+] Feedback CY7C67200 IN Exception Flag (Bit 8) The IN Exception Flag bit indicates when the device received an IN packet when armed for an OUT. 1: Received IN when armed for OUT 0: Received OUT when armed for OUT Stall Flag (Bit 7) The Stall Flag bit indicates that a Stall packet was sent to the host. 1: Stall packet was sent to the host 0: Stall packet was not sent NAK Flag (Bit 6) The NAK Flag bit indicates that a NAK packet was sent to the host. 1: NAK packet was sent to the host 0: NAK packet was not sent Length Exception Flag (Bit 5) The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximum Endpoint Count specified in the Device n Endpoint n Count register. A Length Exception can either mean an overflow or underflow and the Overflow and Underflow flags (bits 11 and 10, respectively) should be checked to determine which event occurred. 1: An overflow or underflow condition occurred 0: An overflow or underflow condition did not occur Setup Flag (Bit 4) The Setup Flag bit indicates that a setup packet was received. In device mode setup packets are stored at memory location 0x0300 for Device 1 and 0x0308 for Device 2. Setup packets are always accepted regardless of the Direction Select and Arm Enable bit settings as long as the Device n EP n Control register Enable bit is set. 1: Setup packet was received 0: Setup packet was not received Sequence Flag (Bit 3) The Sequence Flag bit indicates whether the last data toggle received was a DATA1 or a DATA0. This bit has no effect on receiving data packets; sequence checking must be handled in firmware. 1: DATA1 was received 0: DATA0 was received Timeout Flag (Bit 2) The Timeout Flag bit indicates whether a timeout condition occurred on the last transaction. On the device side, a timeout can occur if the device sends a data packet in response to an IN request but then does not receive a handshake packet in a predetermined time. It can also occur if the device does not receive the data stage of an OUT transfer in time. 1: Timeout occurred 0: Timeout condition did not occur Error Flag (Bit 2) The Error Flag bit is set if a CRC5 and CRC16 error occurs, or if an incorrect packet type is received. Overflow and Underflow are not considered errors and do not affect this bit. 1: Error occurred 0: Error did not occur ACK Flag (Bit 0) The ACK Flag bit indicates whether the last transaction was ACKed. 1: ACK occurred 0: ACK did not occur Document #: 38-08014 Rev. *G Page 32 of 78 [+] Feedback CY7C67200 Device n Endpoint n Count Result Register [R/W] * Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288] * Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298] * Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8] * Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8] * Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8] * Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8] * Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8] * Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8] Figure 34. Device n Endpoint n Count Result Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W X R/W X R/W X R/W X R/W X 7 R/W X 6 R/W X 5 R/W X 4 ...Result R/W X R/W X R/W X R/W X 15 14 13 12 Result... R/W X 3 R/W X 2 R/W X 1 R/W X 0 11 10 9 8 Register Description The Device n Endpoint n Count Result register contains the size difference in bytes between the Endpoint Count specified in the Device n Endpoint n Count register and the last packet received. If an overflow or underflow condition occurs, that is the received packet length differs from the value specified in the Device n Endpoint n Count register, the Length Exception Flag bit in the Device n Endpoint n Status register will be set. The value in this register is only considered when the Length Exception Flag bit is set and the Error Flag bit is not set; both bits are in the Device n Endpoint n Status register. The Device n Endpoint n Count Result register is a memory based register that must be initialized to 0x0000 before USB Device operations are initiated. After initialization, this register must not be written to again. Result (Bits [15:0]) The Result field contains the differences in bytes between the received packet and the value specified in the Device n Endpoint n Count register. If an overflow condition occurs, Result [15:10] is set to `111111', a 2's complement value indicating the additional byte count of the received packet. If an underflow condition occurs, Result [15:0] indicates the excess byte count (number of bytes not used). Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 33 of 78 [+] Feedback CY7C67200 Device n Interrupt Enable Register [R/W] * Device 1 Interrupt Enable Register 0xC08C * Device 2 Interrupt Enable Register 0xC0AC Figure 35. Device n Interrupt Enable Register Bit # 15 VBUS Interrupt Enable R/W 0 7 EP7 Interrupt Enable R/W 0 14 ID Interrupt Enable R/W 0 6 EP6 Interrupt Enable R/W 0 0 5 EP5 Interrupt Enable R/W 0 13 Reserved 12 11 SOF/EOP Timeout Interrupt Enable 0 4 EP4 Interrupt Enable R/W 0 R/W 0 3 EP3 Interrupt Enable R/W 0 2 EP2 Interrupt Enable R/W 0 10 Reserved 9 SOF/EOP Interrupt Enable R/W 0 1 EP1 Interrupt Enable R/W 0 8 Reset Interrupt Enable R/W 0 0 EP0 Interrupt Enable R/W 0 Field Read/Write Default Bit # Field Read/Write Default 0 Register Description The Device n Interrupt Enable register provides control over device-related interrupts including eight different endpoint interrupts. VBUS Interrupt Enable (Bit 15) The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled this interrupt triggers on both the rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Device 1 and is a reserved bit in Device 2. 1: Enable VBUS interrupt 0: Disable VBUS interrupt ID Interrupt Enable (Bit 14) The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Device 1 and is a reserved bit in Device 2. 1: Enable ID interrupt 0: Disable ID interrupt SOF/EOP Timeout Interrupt Enable (Bit 11) The SOF/EOP Timeout Interrupt Enable bit enables or disables the SOF/EOP Timeout Interrupt. When enabled this interrupt triggers when the USB host fails to send a SOF or EOP packet within the time period specified in the Device n SOF/EOP Count register. In addition, the Device n Frame register counts the number of times the SOF/EOP Timeout Interrupt triggers between receiving SOF/EOPs. 1: SOF/EOP timeout occurred 0: SOF/EOP timeout did not occur SOF/EOP Interrupt Enable (Bit 9) The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP received interrupt. 1: Enable SOF/EOP Received interrupt 0: Disable SOF/EOP Received interrupt Reset Interrupt Enable (Bit 8) The Reset Interrupt Enable bit enables or disables the USB Reset Detected interrupt 1: Enable USB Reset Detected interrupt 0: Disable USB Reset Detected interrupt EP7 Interrupt Enable (Bit 7) The EP7 Interrupt Enable bit enables or disables an endpoint seven (EP7) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt. 1: Enable EP7 Transaction Done interrupt 0: Disable EP7 Transaction Done interrupt EP6 Interrupt Enable (Bit 6) The EP6 Interrupt Enable bit enables or disables an endpoint six (EP6) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt. 1: Enable EP6 Transaction Done interrupt 0: Disable EP6 Transaction Done interrupt Document #: 38-08014 Rev. *G Page 34 of 78 [+] Feedback CY7C67200 EP5 Interrupt Enable (Bit 5) The EP5 Interrupt Enable bit enables or disables an endpoint five (EP5) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt. 1: Enable EP5 Transaction Done interrupt 0: Disable EP5 Transaction Done interrupt EP4 Interrupt Enable (Bit 4) The EP4 Interrupt Enable bit enables or disables an endpoint four (EP4) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt. 1: Enable EP4 Transaction Done interrupt 0: Disable EP4 Transaction Done interrupt EP3 Interrupt Enable (Bit 3) The EP3 Interrupt Enable bit enables or disables an endpoint three (EP3) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt. 1: Enable EP3 Transaction Done interrupt 0: Disable EP3 Transaction Done interrupt EP2 Interrupt Enable (Bit 2) The EP2 Interrupt Enable bit enables or disables an endpoint two (EP2) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt. 1: Enable EP2 Transaction Done interrupt 0: Disable EP2 Transaction Done interrupt EP1 Interrupt Enable (Bit 1) The EP1 Interrupt Enable bit enables or disables an endpoint one (EP1) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt. 1: Enable EP1 Transaction Done interrupt 0: Disable EP1 Transaction Done interrupt EP0 Interrupt Enable (Bit 0) The EP0 Interrupt Enable bit enables or disables an endpoint zero (EP0) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt. 1: Enable EP0 Transaction Done interrupt 0: Disable EP0 Transaction Done interrupt Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 35 of 78 [+] Feedback CY7C67200 Device n Address Register [W] * Device 1 Address Register 0xC08E * Device 2 Address Register 0xC0AE Figure 36. Device n Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 7 ...Reserved 0 W 0 W 0 W 0 0 6 0 5 0 4 15 14 13 12 Reserved... 0 3 Address W 0 W 0 W 0 W 0 0 2 0 1 0 0 11 10 9 8 Register Description The Device n Address register holds the device address assigned by the host. This register initializes to the default address 0 at reset but must be updated by firmware when the host assigns a new address. Only USB data sent to the address contained in this register will be responded to, all others are ignored. Address (Bits [6:0]) The Address field contains the USB address of the device assigned by the host. Reserved All reserved bits must be written as `0'. Device n Status Register [R/W] * Device 1 Status Register 0xC090 * Device 2 Status Register 0xC0B0 Figure 37. Device n Status Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 VBUS Interrupt Flag R/W X 7 EP7 Interrupt Flag R/W X 14 ID Interrupt Flag R/W X 6 EP6 Interrupt Flag R/W X X 5 EP5 Interrupt Flag R/W X X 4 EP4 Interrupt Flag R/W X 13 12 Reserved X 3 EP3 Interrupt Flag R/W X X 2 EP2 Interrupt Flag R/W X 11 10 9 SOF/EOP Interrupt Flag R/W X 1 EP1 Interrupt Flag R/W X 8 Reset Interrupt Flag R/W X 0 EP0 Interrupt Flag R/W X Register Description The Device n Status register provides status information for device operation. Pending interrupts can be cleared by writing a `1' to the corresponding bit. This register can be accessed by the HPI interface. VBUS Interrupt Flag (Bit 15) The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Device 1 and is a reserved bit in Device 2. 1: Interrupt triggered 0: Interrupt did not trigger ID Interrupt Flag (Bit 14) The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin. This bit is only available for Device 1 and is a reserved bit in Device 2. 1: Interrupt triggered 0: Interrupt did not trigger SOF/EOP Interrupt Flag (Bit 9) The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP received interrupt has triggered. 1: Interrupt triggered 0: Interrupt did not trigger Page 36 of 78 Document #: 38-08014 Rev. *G [+] Feedback CY7C67200 Reset Interrupt Flag (Bit 8) The Reset Interrupt Flag bit indicates if the USB Reset Detected interrupt has triggered. 1: Interrupt triggered 0: Interrupt did not trigger EP7 Interrupt Flag (Bit 7) The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7) Transaction Done interrupt has triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. 1: Interrupt triggered 0: Interrupt did not trigger EP6 Interrupt Flag (Bit 6) The EP6 Interrupt Flag bit indicates if the endpoint six (EP6) Transaction Done interrupt has triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. 1: Interrupt triggered 0: Interrupt did not trigger EP5 Interrupt Flag (Bit 5) The EP5 Interrupt Flag bit indicates if the endpoint five (EP5) Transaction Done interrupt has triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. 1: Interrupt triggered 0: Interrupt did not trigger EP4 Interrupt Flag (Bit 4) The EP4 Interrupt Flag bit indicates if the endpoint four (EP4) Transaction Done interrupt has triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. 1: Interrupt triggered 0: Interrupt did not trigger EP3 Interrupt Flag (Bit 3) The EP3 Interrupt Flag bit indicates if the endpoint three (EP3) Transaction Done interrupt has triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. 1: Interrupt triggered 0: Interrupt did not trigger EP2 Interrupt Flag (Bit 2) The EP2 Interrupt Flag bit indicates if the endpoint two (EP2) Transaction Done interrupt has triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. 1: Interrupt triggered 0: Interrupt did not trigger EP1 Interrupt Flag (Bit 1) The EP1 Interrupt Flag bit indicates if the endpoint one (EP1) Transaction Done interrupt has triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. 1: Interrupt triggered 0: Interrupt did not trigger EP0 Interrupt Flag (Bit 0) The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0) Transaction Done interrupt has triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's given EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. 1: Interrupt triggered 0: Interrupt did not trigger Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 37 of 78 [+] Feedback CY7C67200 Device n Frame Number Register [R] * Device 1 Frame Number Register 0xC092 * Device 2 Frame Number Register 0xC0B2 Figure 38. Device n Frame Number Register Bit # Field Read/Write Default Bit # Field Read/Write Default R 0 R 0 R 0 R 0 15 SOF/EOP Timeout Flag R 0 7 R 0 6 14 13 SOF/EOP Timeout Interrupt Counter R 0 5 R 0 4 ...Frame R 0 R 0 R 0 R 0 12 11 Reserved 0 3 R 0 2 10 9 Frame... R 0 1 R 0 0 8 Register Description The Device n Frame Number register is a read only register that contains the Frame number of the last SOF packet received. This register also contains a count of SOF/EOP Timeout occurrences. SOF/EOP Timeout Flag (Bit 15) The SOF/EOP Timeout Flag bit indicates when an SOF/EOP Timeout Interrupt occurs. 1: An SOF/EOP Timeout interrupt occurred 0: An SOF/EOP Timeout interrupt did not occur SOF/EOP Timeout Interrupt Counter (Bits [14:12]) The SOF/EOP Timeout Interrupt Counter field increments by 1 from 0 to 7 for each SOF/EOP Timeout Interrupt. This field resets to 0 when a SOF/EOP is received. This field is only updated when the SOF/EOP Timeout Interrupt Enable bit in the Device n Interrupt Enable register is set. Frame (Bits [10:0]) The Frame field contains the frame number from the last received SOF packet in full speed mode. This field has no function for low-speed mode. If a SOF Timeout occurs, this field contains the last received Frame number. Device n SOF/EOP Count Register [W] * Device 1 SOF/EOP Count Register 0xC094 * Device 2 SOF/EOP Count Register 0xC0B4 Figure 39. Device n SOF/EOP Count Register Bit # Field Read/Write Default Bit # Field Read/Write Default R 1 R 1 R 1 R 0 0 7 15 Reserved 0 6 R 1 5 R 0 4 ...Count R 0 R 0 R 0 R 0 R 1 3 14 13 12 11 Count... R 1 2 R 1 1 R 0 0 10 9 8 Register Description The Device n SOF/EOP Count register must be written with the time expected between receiving a SOF/EOPs. If the SOF/EOP counter expires before an SOF/EOP is received, an SOF/EOP Timeout Interrupt can be generated. The SOF/EOP Timeout Interrupt Enable and SOF/EOP Timeout Interrupt Flag are located in the Device n Interrupt Enable and Status registers, respectively. The SOF/EOP count must be set slightly greater than the expected SOF/EOP interval. The SOF/EOP counter decrements at a 12-MHz rate. Therefore in the case of an expected Document #: 38-08014 Rev. *G 1-ms SOF/EOP interval, the SOF/EOP count must be set slightly greater then 0x2EE0. Count (Bits [13:0]) The Count field contains the current value of the SOF/EOP down counter. At power-up and reset, this value is set to 0x2EE0 and for expected 1-ms SOF/EOP intervals, this SOF/EOP count should be increased slightly. Reserved All reserved bits must be written as `0'. Page 38 of 78 [+] Feedback CY7C67200 OTG Control Registers There is one register dedicated for OTG operation. This register is covered in this section and summarized in Table 28. Table 28.OTG Registers Register Name OTG Control Register Address C098H R/W R/W OTG Control Register [0xC098] [R/W] Figure 40. OTG Control Register Bit # Field 15 Reserved 14 13 VBUS Pull-up Enable 0 6 D- Pull-down Enable R/W 0 0 R/W 0 5 12 Receive Disable R/W 0 4 Reserved 11 Charge Pump Enable R/W 0 3 10 VBUS Discharge Enable R/W 0 2 OTG Data Status 0 R X 9 D+ Pull-up Enable R/W 0 1 ID Status R X 8 D- Pull-up Enable R/W 0 0 VBUS Valid Flag R X Read/Write Default Bit # Field 0 7 D+ Pull-down Enable R/W 0 Read/Write Default 0 Register Description The OTG Control register allows control and monitoring over the OTG port on Port1A. VBUS Pull-up Enable (Bit 13) The VBUS Pull-up Enable bit enables or disables a 500 ohm pull-up resistor onto OTG VBus. 1: 500 ohm pull-up resistor enabled 0: 500 ohm pull-up resistor disabled Receive Disable (Bit 12) The Receive Disable bit enables or powers down (disables) the OTG receiver section. 1: OTG receiver powered down and disabled 0: OTG receiver enabled Charge Pump Enable (Bit 11) The Charge Pump Enable bit enables or disables the OTG VBus charge pump. 1: OTG VBus charge pump enabled 0: OTG VBus charge pump disabled VBUS Discharge Enable (Bit 10) The VBUS Discharge Enable bit enables or disables a 2K-ohm discharge pull-down resistor onto OTG VBus. 1: 2K-ohm pull-down resistor enabled 0: 2K-ohm pull-down resistor disabled D+ Pull-up Enable (Bit 9) The D+ Pull-up Enable bit enables or disables a pull-up resistor on the OTG D+ data line. 1: OTG D+ dataline pull-up resistor enabled 0: OTG D+ dataline pull-up resistor disabled Document #: 38-08014 Rev. *G D- Pull-up Enable (Bit 8) The D- Pull-up Enable bit enables or disables a pull-up resistor on the OTG D- data line. 1: OTG D- dataline pull-up resistor enabled 0: OTG D- dataline pull-up resistor disabled D+ Pull-down Enable (Bit 7) The D+ Pull-down Enable bit enables or disables a pull-down resistor on the OTG D+ data line. 1: OTG D+ dataline pull-down resistor enabled 0: OTG D+ dataline pull-down resistor disabled D- Pull-down Enable (Bit 6) The D- Pull-down Enable bit enables or disables a pull-down resistor on the OTG D- data line. 1: OTG D- dataline pull-down resistor enabled 0: OTG D- dataline pull-down resistor disabled OTG Data Status (Bit 2) The OTG Data Status bit is a read only bit and indicates the TTL logic state of the OTG VBus pin. 1: OTG VBus is greater than 2.4V 0: OTG VBus is less than 0.8V ID Status (Bit 1) The ID Status bit is a read only bit that indicates the state of the OTG ID pin on Port A. 1: OTG ID Pin is not connected directly to ground (>10K ohm) 0: OTG ID Pin is connected directly ground (< 10 ohm) Page 39 of 78 [+] Feedback CY7C67200 VBUS Valid Flag (Bit 0) The VBUS Valid Flag bit indicates whether OTG VBus is greater than 4.4V. After turning on VBUS, firmware should wait at least 10 s before this reading this bit. 1: OTG VBus is greater then 4.4V 0: OTG VBus is less then 4.4V Reserved All reserved bits must be written as `0'. GPIO Registers There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized in Table 29. Table 29.GPIO Registers Register Name GPIO Control Register GPIO0 Output Data Register GPIO0 Input Data Register GPIO0 Direction Register GPIO1 Output Data Register GPIO1 Input Data Register GPIO1 Direction Register GPIO Control Register [0xC006] [R/W] Figure 41. GPIO Control Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 Write Protect Enable R/W 0 7 HSS Enable R/W 0 14 Reserved 0 6 Reserved 0 R 0 5 SPI Enable R/W 0 0 13 Reserved 0 4 12 11 SAS Enable R/W 0 3 Reserved 0 0 R/W 0 2 10 9 Mode Select R/W 0 1 Interrupt 0 Polarity Select R/W 0 R/W 0 0 Interrupt 0 Enable R/W 0 8 Address 0xC006 0xC01E 0xC020 0xC022 0xC024 0xC026 0xC028 R/W R/W R/W R R/W R/W R R/W Register Description The GPIO Control register configures the GPIO pins for various interface options. It also controls the polarity of the GPIO interrupt on IRQ0 (GPIO24). Write Protect Enable (Bit 15) The Write Protect Enable bit enables or disables the GPIO write protect. When Write Protect is enabled, the GPIO Mode Select [15:8] bits are read-only until a chip reset. 1: Enable Write Protect 0: Disable Write Protect SAS Enable (Bit 11) The SAS Enable bit, when in SPI mode, reroutes the SPI port SPI_nSSI pin to GPIO[15] rather then GPIO[9]. 1: Reroute SPI_nss to GPIO[15] 0: Leave SPI_nss on GPIO[9] Mode Select (Bits [10:8]) The Mode Select field selects how GPIO[15:0] and GPIO[24:19] are used as defined in Table 30. Table 30.Mode Select Definition Mode Select [10:8] 111 110 101 100 011 010 001 000 GPIO Configuration Reserved SCAN - (HW) Scan diagnostic. For production test only. Not for normal operation HPI - Host Port Interface Reserved Reserved Reserved Reserved GPIO - General Purpose Input Output Document #: 38-08014 Rev. *G Page 40 of 78 [+] Feedback CY7C67200 HSS Enable (Bit 7) The HSS Enable bit routes HSS to GPIO[15:12]. 1: HSS is routed to GPIO 0: HSS is not routed to GPIOs. GPIO[15:12] are free for other purposes. SPI Enable (Bit 5) The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable bit is set, it overrides and routes the SPI_nSSI pin to GPIO15. 1: SPI is routed to GPIO[11:8] 0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other purposes. Interrupt 0 Polarity Select (Bit 1) The Interrupt 0 Polarity Select bit selects the polarity for IRQ0. 1: Sets IRQ0 to rising edge 0: Sets IRQ0 to falling edge Interrupt 0 Enable (Bit 0) The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO bit on the interrupt Enable register must also be set in order for this for this interrupt to be enabled. 1: Enable IRQ0 0: Disable IRQ0 Reserved All reserved bits must be written as `0'. GPIO 0 Output Data Register [0xC01E] [R/W] Figure 42. GPIO 0 Output Data Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 GPIO15 R/W 0 7 GPIO7 R/W 0 14 GPIO14 R/W 0 6 GPIO6 R/W 0 13 GPIO13 R/W 0 5 GPIO5 R/W 0 12 GPIO12 R/W 0 4 GPIO4 R/W 0 11 GPIO11 R/W 0 3 GPIO3 R/W 0 10 GPIO10 R/W 0 2 GPIO2 R/W 0 9 GPIO9 R/W 0 1 GPIO1 R/W 0 8 GPIO8 R/W 0 0 GPIO0 R/W 0 Register Description The GPIO 0 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15 to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data written, not the data on pins configured as inputs (see Input Data Register). Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin. Reserved All reserved bits must be written as `0'. GPIO 1 Output Data Register [0xC024] [R/W] Figure 43. GPIO n Output Data Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 GPIO31 R/W 0 7 GPIO23 R/W 0 14 GPIO30 R/W 0 6 GPIO22 R/W 0 13 GPIO29 R/W 0 5 GPIO21 R/W 0 0 4 GPIO20 R/W 0 0 3 GPIO19 R/W 0 0 12 11 Reserved 0 2 0 1 Reserved 0 0 10 9 8 GPIO24 R/W 0 0 Register Description The GPIO 1 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15 to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data written, not the data on pins configured as inputs (see Input Data Register). Document #: 38-08014 Rev. *G Page 41 of 78 [+] Feedback CY7C67200 Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin. Reserved All reserved bits must be written as `0'. GPIO 0 Input Data Register [0xC020] [R] Figure 44. GPIO 0 Input Data Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 GPIO15 R 0 7 GPIO7 R 0 14 GPIO14 R 0 6 GPIO6 R 0 13 GPIO13 R 0 5 GPIO5 R 0 12 GPIO12 R 0 4 GPIO4 R 0 11 GPIO11 R 0 3 GPIO3 R 0 10 GPIO10 R 0 2 GPIO2 R 0 9 GPIO9 R 0 1 GPIO1 R 0 8 GPIO8 R 0 0 GPIO0 R 0 Register Description The GPIO 0 Input Data register reads the input data of the GPIO pins. The GPIO 0 Input Data register reads from GPIO15 to GPIO0 while the GPIO 1 Input Data register reads from GPIO31 to GPIO19. Every bit represents the voltage of that GPIO pin. GPIO 1 Input Data Register [0xC026] [R] Figure 45. GPIO 1 Input Data Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 GPIO31 R 0 7 GPIO23 R 0 14 GPIO30 R 0 6 GPIO22 R 0 13 GPIO29 R 0 5 GPIO21 R 0 0 4 GPIO20 R 0 0 3 GPIO19 R 0 0 12 11 Reserved 0 2 0 1 Reserved 0 0 10 9 8 GPIO24 R 0 0 Register Description The GPIO 1 Input Data register reads the input data of the GPIO pins. The GPIO 0 Input Data register reads from GPIO15 to GPIO0 while the GPIO 1 Input Data register reads from GPIO31 to GPIO19. Every bit represents the voltage of that GPIO pin. GPIO 0 Direction Register [0xC022] [R/W] Figure 46. GPIO 0 Direction Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 GPIO15 R/W 0 7 GPIO7 R/W 0 14 GPIO14 R/W 0 6 GPIO6 R/W 0 13 GPIO13 R/W 0 5 GPIO5 R/W 0 12 GPIO12 R/W 0 4 GPIO4 R/W 0 11 GPIO11 R/W 0 3 GPIO3 R/W 0 10 GPIO10 R/W 0 2 GPIO2 R/W 0 9 GPIO9 R/W 0 1 GPIO1 R/W 0 8 GPIO8 R/W 0 0 GPIO0 R/W 0 Document #: 38-08014 Rev. *G Page 42 of 78 [+] Feedback CY7C67200 Register Description The GPIO 0 Direction register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction register controls GPIO15 to GPIO0 while the GPIO 1 Direction register controls GPIO31 to GPIO19. When any bit of this register is set to `1', the corresponding GPIO data pin becomes an output. When any bit of this register is set to `0', the corresponding GPIO data pin becomes an input. Reserved All reserved bits must be written as `0'. GPIO 1 Direction Register [0xC028] [R/W] Figure 47. GPIO 1 Direction Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 GPIO31 R/W 0 7 GPIO23 R/W 0 14 GPIO30 R/W 0 6 GPIO22 R/W 0 13 GPIO29 R/W 0 5 GPIO21 R/W 0 R/W 0 4 GPIO20 R/W 0 R/W 0 3 GPIO19 R/W 0 R/W 0 12 11 Reserved R/W 0 2 R/W 0 1 Reserved R/W 0 R/W 0 10 9 8 GPIO24 R/W 0 0 Register Description The GPIO 1 Direction register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction register controls GPIO15 to GPIO0 while the GPIO 1 Direction register controls GPIO31 to GPIO19. When any bit of this register is set to `1', the corresponding GPIO data pin becomes an output. When any bit of this register is set to `0', the corresponding GPIO data pin becomes an input. Reserved All reserved bits must be written as `0'. HSS Registers There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in Table 31. Table 31.HSS Registers Register Name HSS Control Register HSS Baud Rate Register HSS Transmit Gap Register HSS Data Register HSS Receive Address Register HSS Receive Length Register HSS Transmit Address Register HSS Transmit Length Register Address 0xC070 0xC072 0xC074 0xC076 0xC078 0xC07A 0xC07C 0xC07E R/W R/W R/W R/W R/W R/W R/W R/W R/W Document #: 38-08014 Rev. *G Page 43 of 78 [+] Feedback CY7C67200 HSS Control Register [0xC070] [R/W] Figure 48. HSS Control Register Bit # 15 HSS Enable Field Read/Write Default Bit # R/W 0 7 R/W 0 6 R/W 0 5 One Stop Bit R/W 0 4 Transmit Ready R 0 R 0 R/W 0 3 Packet Mode Select R/W 0 R/W 0 2 Receive Overflow Flag R/W 0 14 RTS Polarity Select 13 CTS Polarity Select 12 XOFF 11 XOFF Enable 10 CTS Enable 9 Receive Interrupt Enable R/W 0 1 Receive Packet Ready Flag R 0 8 Done Interrupt Enable R/W 0 0 Receive Ready Flag R 0 Field Read/Write Default Transmit Receive Done Interrupt Done Interrupt Enable Enable R/W 0 R/W 0 Register Description The HSS Control register provides high-level status and control over the HSS port. HSS Enable (Bit 15) The HSS Enable bit enables or disables HSS operation. 1: Enables HSS operation 0: Disables HSS operation RTS Polarity Select (Bit 14) The RTS Polarity Select bit selects the polarity of RTS. 1: RTS is true when LOW 0: RTS is true when HIGH CTS Polarity Select (Bit 13) The CTS Polarity Select bit selects the polarity of CTS. 1: CTS is true when LOW 0: CTS is true when HIGH XOFF (Bit 12) The XOFF bit is a read-only bit that indicates if an XOFF has been received. This bit is automatically cleared when an XON is received. 1: XOFF received 0: XON received XOFF Enable (Bit 11) The XOFF Enable bit enables or disables XON/XOFF software handshaking. 1: Enable XON/XOFF software handshaking 0: Disable XON/XOFF software handshaking CTS Enable (Bit 10) The CTS Enable bit enables or disables CTS/RTS hardware handshaking. 1: Enable CTS/RTS hardware handshaking 0: Disable CTS/RTS hardware handshaking Receive Interrupt Enable (Bit 9) The Receive Interrupt Enable bit enables or disables the Receive Ready and Receive Packet Ready interrupts. 1: Enable the Receive Ready and Receive Packet Ready interrupts 0: Disable the Receive Ready and Receive Packet Ready interrupts Done Interrupt Enable (Bit 8) The Done Interrupt Enable bit enables or disables the Transmit Done and Receive Done interrupts. 1: Enable the Transmit Done and Receive Done interrupts 0: Disable the Transmit Done and Receive Done interrupts Transmit Done Interrupt Flag (Bit 7) The Transmit Done Interrupt Flag bit indicates the status of the Transmit Done Interrupt. It will set when a block transmit is finished. To clear the interrupt, a `1' must be written to this bit. 1: Interrupt triggered 0: Interrupt did not trigger Receive Done Interrupt Flag (Bit 6) The Receive Done Interrupt Flag bit indicates the status of the Receive Done Interrupt. It will set when a block transmit is finished. To clear the interrupt, a `1' must be written to this bit. 1: Interrupt triggered 0: Interrupt did not trigger One Stop Bit (Bit 5) The One Stop Bit bit selects between one and two stop bits for transmit byte mode. In receive mode, the number of stop bits may vary and does not need to be fixed. 1: One stop bit 0: Two stop bits Document #: 38-08014 Rev. *G Page 44 of 78 [+] Feedback CY7C67200 Transmit Ready (Bit 4) The Transmit Ready bit is a read only bit that indicates if the HSS Transmit FIFO is ready for the CPU to load new data for transmission. 1: HSS transmit FIFO ready for loading 0: HSS transmit FIFO not ready for loading Packet Mode Select (Bit 3) The Packet Mode Select bit selects between Receive Packet Ready and Receive Ready as the interrupt source for the RxIntr interrupt. 1: Selects Receive Packet Ready as the source 0: Selects Receive Ready as the source Receive Overflow Flag (Bit 2) The Receive Overflow Flag bit indicates if the Receive FIFO overflowed when set. This flag can be cleared by writing a `1' to this bit. 1: Overflow occurred 0: Overflow did not occur Receive Packet Ready Flag (Bit 1) The Receive Packet Ready Flag bit is a read only bit that indicates if the HSS receive FIFO is full with eight bytes. 1: HSS receive FIFO is full 0: HSS receive FIFO is not full Receive Ready Flag (Bit 0) The Receive Ready Flag is a read only bit that indicates if the HSS receive FIFO is empty. 1: HSS receive FIFO is not empty (one or more bytes is reading for reading) 0: HSS receive FIFO is empty HSS Baud Rate Register [0xC072] [R/W] Figure 49. HSS Baud Rate Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 1 0 7 15 14 Reserved 0 6 0 5 R/W 0 4 ...Baud R/W 0 R/W 1 R/W 1 R/W 1 R/W 0 3 13 12 11 10 Baud... R/W 0 2 R/W 0 1 R/W 0 0 9 8 Register Description The HSS Baud Rate register sets the HSS Baud Rate. At reset, the default value is 0x0017 which sets the baud rate to 2.0 MHz. Baud (Bits [12:0]) The Baud field is the baud rate divisor minus one, in units of 1/48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts a constraint on the Baud Value as follows: (24 - 1) < Baud > (5000 - 1) Reserved All reserved bits must bit written as `0'. Document #: 38-08014 Rev. *G Page 45 of 78 [+] Feedback CY7C67200 HSS Transmit Gap Register [0xC074] [R/W] Figure 50. HSS Transmit Gap Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 0 4 R/W 0 15 14 13 12 Reserved 0 3 R/W 1 0 2 R/W 0 0 1 R/W 0 0 0 R/W 1 11 10 9 8 Transmit Gap Select Register Description The HSS Transmit Gap register is only valid in block transmit mode. It allows for a programmable number of stop bits to be inserted thus overwriting the One Stop Bit in the HSS Control register. The default reset value of this register is 0x0009, equivalent to two stop bits. Transmit Gap Select (Bits [7:0]) The Transmit Gap Select field sets the inactive time between transmitted bytes. The inactive time = (Transmit Gap Select - 7) * bit time. Therefore an Transmit Gap Select Value of 8 is equal to having one Stop bit. Reserved All reserved bits must be written as `0'. HSS Data Register [0xC076] [R/W] Figure 51. HSS Data Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W X R/W X R/W X R/W X X 7 X 6 X 5 X 4 Data R/W X R/W X R/W X R/W X 15 14 13 12 Reserved X 3 X 2 X 1 X 0 11 10 9 8 Register Description The HSS Data register contains data received on the HSS port (not for block receive mode) when read. This receive data is valid when the Receive Ready bit of the HSS Control register is set to `1'. Writing to this register initiates a single byte transfer of data. The Transmit Ready Flag in the HSS Control register must read `1' before writing to this register (this avoids disrupting the previous/current transmission). Data (Bits [7:0]) The Data field contains the data received or to be transmitted on the HSS port. Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 46 of 78 [+] Feedback CY7C67200 HSS Receive Address Register [0xC078] [R/W] Figure 52. HSS Receive Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8 Register Description The HSS Receive Address register is used as the base pointer address for the next HSS block receive transfer. Address (Bits [15:0]) The Address field sets the base pointer address for the next HSS block receive transfer. HSS Receive Counter Register [0xC07A] [R/W] Figure 53. HSS Receive Counter Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 15 14 13 Reserved 0 4 ...Counter R/W 0 R/W 0 R/W 0 R/W 0 0 3 0 2 R/W 0 1 12 11 10 9 Counter... R/W 0 0 8 Register Description The HSS Receive Counter register designates the block byte length for the next HSS receive transfer. This register must be loaded with the word count minus one to start the block receive transfer. As each byte is received this register value is decremented. When read, this register indicates the remaining length of the transfer. Counter (Bits [9:0]) The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When the transfer is complete this register returns 0x03FF until reloaded. Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 47 of 78 [+] Feedback CY7C67200 HSS Transmit Address Register [0xC07C] [R/W] Figure 54. HSS Transmit Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8 Register Description The HSS Transmit Address register is used as the base pointer address for the next HSS block transmit transfer. Address (Bits [15:0]) The Address field sets the base pointer address for the next HSS block transmit transfer. HSS Transmit Counter Register [0xC07E] [R/W] Figure 55. HSS Transmit Counter Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 15 14 13 Reserved 0 4 ...Counter R/W 0 R/W 0 R/W 0 R/W 0 0 3 0 2 R/W 0 1 12 11 10 9 Counter... R/W 0 0 8 Register Description The HSS Transmit Counter register designates the block byte length for the next HSS transmit transfer. This register must be loaded with the word count minus one to start the block transmit transfer. As each byte is transmitted this register value is decremented. When read, this register indicates the remaining length of the transfer. Counter (Bits [9:0]) The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When the transfer is complete this register returns 0x03FF until reloaded. Reserved All reserved bits must be written as `0'. HPI Registers There are five registers dedicated to HPI operation. In addition, there is an HPI status port which can be address over HPI. Each of these registers is covered in this section and are summarized in Table 32. Table 32.HPI Registers Register Name HPI Breakpoint Register Interrupt Routing Register SIE1msg Register SIE2msg Register HPI Mailbox Register Address 0x0140 0x0142 0x0144 0x0148 0xC0C6 R/W R R W W R/W Document #: 38-08014 Rev. *G Page 48 of 78 [+] Feedback CY7C67200 HPI Breakpoint Register [0x0140] [R] Figure 56. HPI Breakpoint Register Bit # Field Read/Write Default Bit # Field Read/Write Default R 0 R 0 R 0 R 0 R 0 7 R 0 6 R 0 5 R 0 4 ...Address R 0 R 0 R 0 R 0 15 14 13 12 Address... R 0 3 R 0 2 R 0 1 R 0 0 11 10 9 8 Register Description The HPI Breakpoint register is a special on-chip memory location, which the external processor can access using normal HPI memory read/write cycles. This register is read-only by the CPU but is read/write by the HPI port. The contents of this register have the same effect as the Breakpoint register [0xC014]. This special Breakpoint register is used by software debuggers which interface through the HPI port instead of the serial port. When the program counter matches the Breakpoint Address, the INT127 interrupt triggers. To clear this interrupt, a zero value must be written to this register. Address (Bits [15:0]) The Address field is a 16-bit field containing the breakpoint address. Interrupt Routing Register [0x0142] [R] Figure 57. Interrupt Routing Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 VBUS to HPI Enable R 0 7 Resume2 to HPI Enable 0 14 ID to HPI Enable R 0 6 Resume1 to HPI Enable 0 0 13 12 11 10 9 8 HPI Swap 1 Enable R 0 0 HPI Swap 0 Enable 0 SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Enable CPU Enable HPI Enable CPU Enable Enable R 0 5 Reserved 0 R 1 4 R 0 3 Done2 to HPI Enable 0 R 1 2 R 0 1 Done1 to HPI Reset1 to HPI Enable Enable 0 0 Register Description The Interrupt Routing register allows the HPI port to take over some or all of the SIE interrupts that usually go to the on-chip CPU. This register is read-only by the CPU but is read/write by the HPI port. By setting the appropriate bit to `1', the SIE interrupt is routed to the HPI port to become the HPI_INTR signal and also readable in the HPI Status register. The bits in this register select where the interrupts are routed. The individual interrupt enable is handled in the SIE interrupt enable register. VBUS to HPI Enable (Bit 15) The VBUS to HPI Enable bit routes the OTG VBUS interrupt to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port ID to HPI Enable (Bit 14) The ID to HPI Enable bit routes the OTG ID interrupt to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port SOF/EOP2 to HPI Enable (Bit 13) The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt to the HPI port. 1: Route signal to HPI port 0: Do not route signal to HPI port Document #: 38-08014 Rev. *G Page 49 of 78 [+] Feedback CY7C67200 SOF/EOP2 to CPU Enable (Bit 12) The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2 interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can be routed to both the on-chip CPU and the HPI port the firmware must ensure only one of the two (CPU, HPI) resets the interrupt. 1: Route signal to CPU 0: Do not route signal to CPU SOF/EOP1 to HPI Enable (Bit 11) The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt to the HPI port. 1: Route signal to HPI port 0: Do not route signal to HPI port SOF/EOP1 to CPU Enable (Bit 10) The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1 interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can be routed to both the on-chip CPU and the HPI port the firmware must ensure only one of the two (CPU, HPI) resets the interrupt. 1: Route signal to CPU 0: Do not route signal to CPU Reset2 to HPI Enable (Bit 9) The Reset2 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 2 to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port HPI Swap 1 Enable (Bit 8) Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to `00', the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to `11', the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8]. Resume2 to HPI Enable (Bit 7) The Resume2 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 2 to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port Resume1 to HPI Enable (Bit 6) The Resume1 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 1 to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port Done2 to HPI Enable (Bit 3) The Done2 to HPI Enable bit routes the Done interrupt for Host/Device 2 to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port Done1 to HPI Enable (Bit 2) The Done1 to HPI Enable bit routes the Done interrupt for Host/Device 1 to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port Reset1 to HPI Enable (Bit 1) The Reset1 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 1 to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port HPI Swap 0 Enable (Bit 0) Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to `00', the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to `11', the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8]. Document #: 38-08014 Rev. *G Page 50 of 78 [+] Feedback CY7C67200 SIEXmsg Register [W] * SIE1msg Register 0x0144 * SIE2msg Register 0x0148 Figure 58. SIEXmsg Register Bit # Field Read/Write Default Bit # Field Read/Write Default W X W X W X W X W X 7 W X 6 W X 5 W X 4 ...Data W X W X W X W X 15 14 13 12 Data... W X 3 W X 2 W X 1 W X 0 11 10 9 8 Register Description The SIEXmsg register allows an interrupt to be generated on the HPI port. Any write to this register causes the SIEXmsg flag in the HPI Status Port to go high and also causes an interrupt on the HPI_INTR pin. The SIEXmsg flag is automatically cleared when the HPI port reads from this register. Data (Bits [15:0]) The Data field[15:0] simply must have any value written to it to cause SIExmsg flag in the HPI Status Port to go high. HPI Mailbox Register [0xC0C6] [R/W] Figure 59. HPI Mailbox Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Message R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Message... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8 Register Description The HPI Mailbox register provides a common mailbox between the CY7C67200 and the external host processor. If enabled, the HPI Mailbox RX Full interrupt triggers when the external host processor writes to this register. When the CY7C67200 reads this register the HPI Mailbox RX Full interrupt automatically gets cleared. If enabled, the HPI Mailbox TX Empty interrupt triggers when the external host processor reads from this register. The HPI Mailbox TX Empty interrupt is automatically cleared when the CY7C67200 writes to this register. In addition, when the CY7C67200 writes to this register, the HPI_INTR signal on the HPI port asserts signaling the external processor that there is data in the mailbox to read. The HPI_INTR signal deasserts when the external host processor reads from this register. Message (Bits [15:0]) The Message field contains the message that the host processor wrote to the HPI Mailbox register. Document #: 38-08014 Rev. *G Page 51 of 78 [+] Feedback CY7C67200 HPI Status Port [] [HPI: R] Figure 60. HPI Status Port Bit # Field Read/Write Default Bit # Field Read/Write Default 15 VBUS Flag R X 7 Resume2 Flag R X 14 ID Flag R X 6 Resume1 Flag R X 13 Reserved X 5 SIE2msg R X 12 SOF/EOP2 Flag R X 4 11 Reserved X 3 Done2 Flag R X 10 SOF/EOP1 Flag R X 2 Done1 Flag R X 9 Reset2 Flag R X 1 Reset1 Flag R X 8 Mailbox In Flag R X 0 Mailbox Out Flag R X SIE1msg R X Register Description The HPI Status Port provides the external host processor with the MailBox status bits plus several SIE status bits. This register is not accessible from the on-chip CPU. The additional SIE status bits are provided to aid external device driver firmware development, and are not recommended for applications that do not have an intimate relationship with the on-chip BIOS. Reading from the HPI Status Port does not result in a CPU HPI interface memory access cycle. The external host may continuously poll this register without degrading the CPU or DMA performance. VBUS Flag (Bit 15) The VBUS Flag bit is a read-only bit that indicates whether OTG VBus is greater than 4.4V. After turning on VBUS, firmware should wait at least 10 s before this reading this bit. 1: OTG VBus is greater then 4.4V 0: OTG VBus is less then 4.4V ID Flag (Bit 14) The ID Flag bit is a read-only bit that indicates the state of the OTG ID pin. SOF/EOP2 Flag (Bit 12) The SOF/EOP2 Flag bit is a read-only bit that indicates if a SOF/EOP interrupt occurs on either Host/Device 2. 1: Interrupt triggered 0: Interrupt did not trigger SOF/EOP1 Flag (Bit 10) The SOF/EOP1 Flag bit is a read-only bit that indicates if a SOF/EOP interrupt occurs on either Host/Device 1. 1: Interrupt triggered 0: Interrupt did not trigger Reset2 Flag (Bit 9) The Reset2 Flag bit is a read-only bit that indicates if a USB Reset interrupt occurs on either Host/Device 2. 1: Interrupt triggered 0: Interrupt did not trigger Document #: 38-08014 Rev. *G Mailbox In Flag (Bit 8) The Mailbox In Flag bit is a read-only bit that indicates if a message is ready in the incoming mailbox. This interrupt clears when on-chip CPU reads from the HPI Mailbox register. 1: Interrupt triggered 0: Interrupt did not trigger Resume2 Flag (Bit 7) The Resume2 Flag bit is a read-only bit that indicates if a USB resume interrupt occurs on either Host/Device 2. 1: Interrupt triggered 0: Interrupt did not trigger Resume1 Flag (Bit 6) The Resume1 Flag bit is a read-only bit that indicates if a USB resume interrupt occurs on either Host/Device 1. 1: Interrupt triggered 0: Interrupt did not trigger SIE2msg (Bit 5) The SIE2msg Flag bit is a read-only bit that indicates if the CY7C67200 CPU has written to the SIE2msg register. This bit is cleared on an HPI read. 1: The SIE2msg register has been written by the CY7C67200 CPU 0: The SIE2msg register has not been written by the CY7C67200 CPU SIE1msg (Bit 4) The SIE1msg Flag bit is a read-only bit that indicates if the CY7C67200 CPU has written to the SIE1msg register. This bit is cleared on an HPI read. 1: The SIE1msg register has been written by the CY7C67200 CPU 0: The SIE1msg register has not been written by the CY7C67200 CPU Done2 Flag (Bit 3) In host mode the Done2 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 2. In device Page 52 of 78 [+] Feedback CY7C67200 mode this read only bit indicates if any of the endpoint interrupts occurs on Device 2. Firmware needs to determine which endpoint interrupt occurred. 1: Interrupt triggered 0: Interrupt did not trigger Done1 Flag (Bit 2) In host mode the Done 1 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 1. In device mode this read-only bit indicates if any of the endpoint interrupts occurs on Device 1. Firmware needs to determine which endpoint interrupt occurred. 1: Interrupt triggered 0: Interrupt did not trigger Reset1 Flag (Bit 1) The Reset1 Flag bit is a read-only bit that indicates if a USB Reset interrupt occurs on either Host/Device 1. 1: Interrupt triggered 0: Interrupt did not trigger Mailbox Out Flag (Bit 0) The Mailbox Out Flag bit is a read-only bit that indicates if a message is ready in the outgoing mailbox. This interrupt clears when the external host reads from the HPI Mailbox register. 1: Interrupt triggered 0: Interrupt did not trigger SPI Registers There are 12 registers dedicated to SPI operation. Each register is covered in this section and summarized in Table 33. Table 33.SPI Registers Register Name SPI Configuration Register SPI Control Register SPI Interrupt Enable Register SPI Status Register SPI Interrupt Clear Register SPI CRC Control Register SPI CRC Value SPI Data Register SPI Transmit Address Register SPI Transmit Count Register SPI Receive Address Register SPI Receive Count Register SPI Configuration Register [0xC0C8] [R/W] Figure 61. SPI Configuration Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 3Wire Enable R/W 1 7 Master Active Enable R 0 14 Phase Select R/W 0 6 Master Enable R/W 0 13 SCK Polarity Select R/W 0 5 SS Enable R/W 0 R/W 1 R/W 1 R/W 0 4 0 3 12 11 Scale Select R/W R/W 0 2 SS Delay Select R/W 1 R/W 1 R/W 1 R/W 0 1 10 9 8 Reserved 0 0 Address 0xC0C8 0xC0CA 0xC0CC 0xC0CE 0xC0D0 0xC0D2 0xC0D4 0xC0D6 0xC0D8 0xC0DA 0xC0DC 0xC0DE R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W Register Description The SPI Configuration register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted. Document #: 38-08014 Rev. *G Page 53 of 78 [+] Feedback CY7C67200 3Wire Enable (Bit 15) The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowing only half duplex operation. 1: MISO and MOSI data lines are tied together 0: Normal MISO and MOSI Full Duplex operation (not tied together) Phase Select (Bit 14) The Phase Select bit selects advanced or delayed SCK phase. This field only applies to master mode. 1: Advanced SCK phase 0: Delayed SCK phase SCK Polarity Select (Bit 13) This SCK Polarity Select bit selects the polarity of SCK. 1: Positive SCK polarity 0: Negative SCK polarity Scale Select (Bits [12:9]) The Scale Select field provides control over the SCK frequency, based on 48 MHz. See Table 34 for a definition of this field. This field only applies to master mode. Table 34.Scale Select Field Definition for SCK Frequency Scale Select [12:9] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SCK Frequency 12 MHz 8 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1.5 MHz 1 MHz 750 KHz 500 KHz 375 KHz 250 KHz 375 KHz 250 KHz 375 KHz 250 KHz Master Active Enable (Bit 7) The Master Active Enable bit is a read-only bit that indicates if the master state machine is active or idle. This field only applies to master mode. 1: Master state machine is active 0: Master state machine is idle Master Enable (Bit 6) The Master Enable bit sets the SPI interface to master or slave. This bit is only writable when the Master Active Enable bit reads `0', otherwise value will not change. 1: Master SPI interface 0: Slave SPI interface SS Enable (Bit 5) The SS Enable bit enables or disables the master SS output. 1: Enable master SS output 0: Disable master SS output (three-state master SS output, for single SS line in slave mode) SS Delay Select (Bits [4:0]) When the SS Delay Select field is set to `00000' this indicates manual mode. In manual mode SS is controlled by the SS Manual bit of the SPI Control register. When the SS Delay Select field is set between `00001' to `11111', this value indicates the count in half bit times of auto transfer delay for: SS LOW to SCK active, SCK inactive to SS HIGH, SS HIGH time. This field only applies to master mode. Document #: 38-08014 Rev. *G Page 54 of 78 [+] Feedback CY7C67200 SPI Control Register [0xC0CA] [R/W] Figure 62. SPI Control Register Bit # Field Read/Write Default Bit # Field Read/Write Default 15 SCK Strobe W 0 7 Transmit Empty R 1 14 FIFO Init W 0 6 Receive Full R 0 R/W 0 13 Byte Mode R/W 0 5 12 Full Duplex R/W 0 4 Transmit Bit Length R/W 0 R/W 0 R/W 0 11 SS Manual R/w 0 3 10 Read Enable R/W 0 2 9 Transmit Ready R 0 1 Receive Bit Length R/w 0 R/W 0 8 Receive Data Ready R 1 0 Register Description The SPI Control register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted. SCK Strobe (Bit 15) The SCK Strobe bit starts the SCK strobe at the selected frequency and polarity (set in the SPI Configuration register), but not phase. This bit feature can only be enabled when in master mode and must be during a period of inactivity. This bit is self-clearing. 1: SCK Strobe Enable 0: No Function FIFO Init (Bit 14) The FIFO Init bit initializes the FIFO and clear the FIFO Error Status bit. This bit is self-clearing. 1: FIFO Init Enable 0: No Function Byte Mode (Bit 13) The Byte Mode bit selects between PIO (byte mode) and DMA (block mode) operation. 1: Set PIO (byte mode) operation 0: Set DMA (block mode) operation Full Duplex (Bit 12) The Full Duplex bit selects between full-duplex and half-duplex operation. 1: Enable full duplex. Full duplex is not allowed and will not set if the 3Wire Enable bit of the SPI Configuration register is set to `1' 0: Enable half-duplex operation SS Manual (Bit 11) The SS Manual bit activates or deactivates SS if the SS Delay Select field of the SPI Control register is all zeros and is configured as master interface. This field only applies to master mode. 1: Activate SS, master drives SS line asserted LOW 0: Deactivate SS, master drives SS line deasserted HIGH Read Enable (Bit 10) The Read Enable bit initiates a read phase for a master mode transfer or set the slave to receive (in slave mode). 1: Initiates a read phase for a master transfer or sets a slave to receive. In master mode this bit is sticky and remains set until the read transfer begins. 0: Initiates the write phase for slave operation Transmit Ready (Bit 9) The Transmit Ready bit is a read-only bit that indicates if the transmit port is ready to empty and ready to be written. 1: Ready for data to be written to the port. The transmit FIFO is not full. 0: Not ready for data to be written to the port Receive Data Ready (Bit 8) The Receive Data Ready bit is a read-only bit that indicates if the receive port has data ready. 1: Receive port has data ready to read 0: Receive port does not have data ready Transmit Empty (Bit 7) The Transmit Empty bit is a read-only bit that indicates if the transmit FIFO is empty. 1: Transmit FIFO is empty 0: Transmit FIFO is not empty Receive Full (Bit 6) The Receive Full bit is a read-only bit that indicates if the receive FIFO is full. 1: Receive FIFO is full 0: Receive FIFO is not full Transmit Bit Length (Bits [5:3]) The Transmit Bit Length field controls whether a full byte or partial byte is to be transmitted. If Transmit Bit Length is `000', a full byte is transmitted. If Transmit Bit Length is `001' to `111', the value indicates the number of bits that will be transmitted. Document #: 38-08014 Rev. *G Page 55 of 78 [+] Feedback CY7C67200 Receive Bit Length (Bits [2:0]) The Receive Bit Length field controls whether a full byte or partial byte will be received. If Receive Bit Length is `000' then a full byte will be received. If Receive Bit Length is `001' to `111', then the value indicates the number of bits that will be received. SPI Interrupt Enable Register [0xC0CC] [R/W] Figure 63. SPI Interrupt Enable Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 0 0 7 0 6 0 5 ...Reserved 0 4 0 3 15 14 13 12 Reserved... 0 2 Receive Interrupt Enable R/W 0 0 1 Transmit Interrupt Enable R/W 0 0 0 Transfer Interrupt Enable R/W 0 0 11 10 9 8 Register Description The SPI Interrupt Enable register controls the SPI port. Receive Interrupt Enable (Bit 2) The Receive Interrupt Enable bit enables or disables the byte mode receive interrupt (RxIntVal). 1: Enable byte mode receive interrupt 0: Disable byte mode receive interrupt Transmit Interrupt Enable (Bit 1) The Transmit Interrupt Enable bit enables or disables the byte mode transmit interrupt (TxIntVal). SPI Status Register [0xC0CE] [R] 1: Enables byte mode transmit interrupt 0: Disables byte mode transmit interrupt Transfer Interrupt Enable (Bit 0) The Transfer Interrupt Enable bit enables or disables the block mode interrupt (XfrBlkIntVal). 1: Enables block mode interrupt 0: Disables block mode interrupt Reserved All reserved bits must be written as `0'. Figure 64. SPI Status Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 7 FIFO Error Flag R 0 0 0 0 6 0 5 Reserved 0 0 0 4 15 14 13 12 Reserved 0 3 0 2 Receive Interrupt Flag R 0 0 1 Transmit Interrupt Flag R 0 0 0 Transfer Interrupt Flag R 0 11 10 9 8 Register Description The SPI Status register is a read only register that provides status for the SPI port. FIFO Error Flag (Bit 7) The FIFO Error Flag bit is a read only bit that indicates if a FIFO error occurred. When this bit is set to `1' and the Transmit Empty bit of the SPI Control register is set to `1', then a Tx FIFO underflow has occurred. Similarly, when set with the Receive Full bit of the SPI Control register, a Rx FIFO overflow has occured.This bit automatically clear when the SPI FIFO Init Enable bit of the SPI Control register is set. 1: Indicates FIFO error 0: Indicates no FIFO error Receive Interrupt Flag (Bit 2) The Receive Interrupt Flag is a read only bit that indicates if a byte mode receive interrupt has triggered. 1: Indicates a byte mode receive interrupt has triggered 0: Indicates a byte mode receive interrupt has not triggered Page 56 of 78 Document #: 38-08014 Rev. *G [+] Feedback CY7C67200 Transmit Interrupt Flag (Bit 1) The Transmit Interrupt Flag is a read only bit that indicates a byte mode transmit interrupt has triggered. 1: Indicates a byte mode transmit interrupt has triggered 0: Indicates a byte mode transmit interrupt has not triggered SPI Interrupt Clear Register [0xC0D0] [W] Transfer Interrupt Flag (Bit 0) The Transfer Interrupt Flag is a read only bit that indicates a block mode interrupt has triggered. 1: Indicates a block mode interrupt has triggered 0: Indicates a block mode interrupt has not triggered Figure 65. SPI Interrupt Clear Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 0 0 0 0 7 0 6 0 5 Reserved 0 4 15 14 13 12 Reserved 0 3 0 2 0 1 0 0 11 10 9 8 Transmit Transfer Interrupt Clear Interrupt Clear W 0 W 0 Register Description The SPI Interrupt Clear register is a write-only register that allows the SPI Transmit and SPI Transfer Interrupts to be cleared. Transmit Interrupt Clear (Bit 1) The Transmit Interrupt Clear bit is a write-only bit that clears the byte mode transmit interrupt. This bit is self-clearing. 1: Clear the byte mode transmit interrupt 0: No function SPI CRC Control Register [0xC0D2] [R/W] Transfer Interrupt Clear (Bit 0) The Transfer Interrupt Clear bit is a write-only bit that will clear the block mode interrupt. This bit is self clearing. 1: Clear the block mode interrupt 0: No function Reserved All reserved bits must be written as `0'. Figure 66. SPI CRC Control Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 0 R/W 0 7 R/W 0 6 15 CRC Mode 14 13 CRC Enable R/W 0 5 12 CRC Clear R/W 0 4 ...Reserved 0 0 0 0 11 Receive CRC R/W 0 3 10 One in CRC R 0 2 9 Zero in CRC R 0 1 8 Reserved... 0 0 Register Description The SPI CRC Control register provides control over the CRC source and polynomial value. CRC Mode (Bits [15:14) The CRCMode field selects the CRC polynomial as defined in Table 35. Table 35.CRC Mode Definition CRCMode [9:8] 00 01 10 11 Document #: 38-08014 Rev. *G CRC Polynomial MMC 16-bit: X^16 + X^12 + X^5 + 1 (CCITT Standard) CRC7 7-bit: X^7+ X^3 + 1 MST 16-bit: X^16+ X^15 + X^2 + 1 Reserved, 16-bit polynomial 1. Page 57 of 78 [+] Feedback CY7C67200 CRC Enable (Bit 13) The CRC Enable bit enables or disables the CRC operation. 1: Enables CRC operation 0: Disables CRC operation CRC Clear (Bit 12) The CRC Clear bit will clear the CRC with a load of all ones. This bit is self clearing and always reads `0'. 1: Clear CRC with all ones 0: No Function Receive CRC (Bit 11) The Receive CRC bit determines whether the receive bit stream or the transmit bit stream is used for the CRC data input in full duplex mode. This bit is a don't care in half-duplex mode. 1: Assigns the receive bit stream 0: Assigns the transmit bit stream SPI CRC Value Register [0xC0D4] [R/W] One in CRC (Bit 10) The One in CRC bit is a read-only bit that indicates if the CRC value is all zeros or not. 1: CRC value is not all zeros 0: CRC value is all zeros Zero in CRC (Bit 9) The Zero in CRC bit is a read-only bit that indicates if the CRC value is all ones or not. 1: CRC value is not all ones 0: CRC value is all ones Reserved All reserved bits must be written as `0'. Figure 67. SPI CRC Value Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 ...CRC R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 CRC... R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 11 10 9 8 Register Description The SPI CRC Value register contains the CRC value. CRC (Bits [15:0]) The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value will be a seven bit value [6:0]. Therefore bits [15:7] are invalid in CRC7 mode. SPI Data Register [0xC0D6] [R/W] Figure 68. SPI Data Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W X R/W X R/W X R/W X X 7 X 6 X 5 X 4 Data R/W X R/W X R/W X R/W X 15 14 13 12 Reserved X 3 X 2 X 1 X 0 11 10 9 8 Register Description The SPI Data register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO byte mode. This receive data is valid when the receive bit of the SPI Interrupt Value is set to `1' (RxIntVal triggers) or the Receive Document #: 38-08014 Rev. *G Page 58 of 78 [+] Feedback CY7C67200 Data Ready bit of the SPI Control register is set to `1'. Writing to this register in PIO byte mode will initiate a transfer of data, the number of bits defined by Transmit Bit Length field in the SPI Control register. Data (Bits [7:0]) The Data field contains data received or to be transmitted on the SPI port. Reserved All reserved bits must be written as `0'. SPI Transmit Address Register [0xC0D8] [R/W] Figure 69. SPI Transmit Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8 Register Description The SPI Transmit Address register is used as the base address for the SPI transmit DMA. Address (Bits [15:0]) The Address field sets the base address for the SPI transmit DMA. SPI Transmit Count Register [0xC0DA] [R/W] Figure 70. SPI Transmit Count Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 15 14 13 Reserved 0 5 0 4 ...Count R/W 0 R/W 0 R/W 0 R/W 0 0 3 R/W 0 2 12 11 10 9 Count... R/W 0 1 R/W 0 0 8 Register Description The SPI Transmit Count register designates the block byte length for the SPI transmit DMA transfer. Count (Bits [10:0]) The Count field sets the count for the SPI transmit DMA transfer. Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 59 of 78 [+] Feedback CY7C67200 SPI Receive Address Register [0xC0DC [R/W] Figure 71. SPI Receive Address Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8 Register Description The SPI Receive Address register is issued as the base address for the SPI Receive DMA. Address (Bits [15:0]) The Address field sets the base address for the SPI receive DMA. SPI Receive Count Register [0xC0DE] [R/W] Figure 72. SPI Receive Count Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 15 14 13 Reserved 0 5 0 4 ...Count R/W 0 R/W 0 R/W 0 R/W 0 0 3 R/W 0 2 12 11 10 9 Count... R/W 0 1 R/W 0 0 8 Register Description The SPI Receive Count register designates the block byte length for the SPI receive DMA transfer. Count (Bits [10:0]) The Count field sets the count for the SPI receive DMA transfer. Reserved All reserved bits must be written as `0'. UART Registers There are three registers dedicated to UART operation. Each of these registers is covered in this section and summarized in Table 36. Table 36.UART Registers Register Name UART Control Register UART Status Register UART Data Register Address 0xC0E0 0xC0E2 0xC0E4 R/W R/W R R/W Document #: 38-08014 Rev. *G Page 60 of 78 [+] Feedback CY7C67200 UART Control Register [0xC0E0] [R/W] Figure 73. UART Control Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 0 7 0 6 ...Reserved 0 5 0 4 Scale Select R/W 0 R/W 0 15 14 13 12 Reserved... 0 3 0 2 Baud Select R/W 1 R/W 1 0 1 0 0 UART Enable R/W 1 11 10 9 8 Register Description The UART Control register enables or disables the UART allowing GPIO7 (UART_TXD) and GPIO6 (UART_RXD) to be freed up for general use. This register must also be written to set the baud rate, which is based on a 48-MHz clock. Scale Select (Bit 4) The Scale Select bit acts as a prescaler that will divide the baud rate by eight. 1: Enable prescaler 0: Disable prescaler Baud Select (Bits [3:1]) Refer to Table 37 for a definition of this field. Table 37.UART Baud Select Definition Baud Select [3:1] 000 001 010 011 100 101 110 111 UART Enable (Bit 0) The UART Enable bit enables or disables the UART. 1: Enable UART 0: Disable UART. This allows GPIO6 and GPIO7 to be used for general use Reserved All reserved bits must be written as `0'. Baud Rate w/DIV8 = 0 115.2K baud 57.6K baud 38.4K baud 28.8K baud 19.2K baud 14.4K baud 9.6K baud 7.2K baud Baud Rate w/DIV8 = 1 14.4K baud 7.2K baud 4.8K baud 3.6K baud 2.4K baud 1.8K baud 1.2K baud 0.9K baud UART Status Register [0xC0E2] [R] Figure 74. UART Status Register Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 0 7 6 0 5 ...Reserved 0 0 0 0 4 0 3 15 14 13 12 Reserved... 0 2 0 1 Receive Full R 0 0 0 Transmit Full R 0 0 11 10 9 8 Register Description The UART Status register is a read-only register that indicates the status of the UART buffer. Document #: 38-08014 Rev. *G Page 61 of 78 [+] Feedback CY7C67200 Receive Full (Bit 1) The Receive Full bit indicates whether the receive buffer is full. It can be programmed to interrupt the CPU as interrupt #5 when the buffer is full. This can be done though the UART bit of the Interrupt Enable register (0xC00E). This bit will automatically be cleared when data is read from the UART Data register. 1: Receive buffer full 0: Receive buffer empty UART Data Register [0xC0E4] [R/W] Transmit Full (Bit 0) The Transmit Full bit indicates whether the transmit buffer is full. It can be programmed to interrupt the CPU as interrupt #4 when the buffer is empty. This can be done though the UART bit of the Interrupt Enable register (0xC00E). This bit will automatically be set to `1' after data is written by EZ-Host to the UART Data register (to be transmitted). This bit will automatically be cleared to `0' after the data is transmitted. 1: Transmit buffer full (transmit busy) 0: Transmit buffer is empty and ready for a new byte of data Figure 75. UART Data Register Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 0 4 Data R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Reserved 0 3 0 2 0 1 0 0 11 10 9 8 Register Description The UART Data register contains data to be transmitted or received from the UART port. Data written to this register will start a data transmission and also causes the UART Transmit Empty Flag of the UART Status register to set. When data received on the UART port is read from this register, the UART Receive Full Flag of the UART Status register will be cleared. Data (Bits [7:0]) The Data field is where the UART data to be transmitted or received is located Reserved All reserved bits must be written as `0'. Document #: 38-08014 Rev. *G Page 62 of 78 [+] Feedback CY7C67200 Pin Diagram The following describes the CY7C67200 48-pin FBGA. Figure 76. EZ-OTG Pin Diagram A1 GND A2 GPIO1/D1 A3 GPIO3/D3 A4 VCC A5 nRESET A6 Reserved B6 GND B1 AGND B2 GPIO0/D0 B3 GPIO4/D4 B4 GPIO6/D6/RX B5 GPIO7/D7/TX C1 OTGVBUS D1 CSWITCHA E1 BOOSTGND F1 BOOSTVCC C2 DM2A D2 CSWITCHB E2 VSWITCH F2 DM1A C3 GPIO2/D2 D3 DP2A E3 DP1A F3 GPIO30/SDA C4 GPIO5/D5 D4 GPIO11/D1/ MOSI E4 GPIO14/D14/ RTS F4 GPIO29/ OTGID G4 GPIO23/nRD/ nWAIT H4 GPIO24/INT/ IRQ0 C5 GPIO8/D8/ MISO D5 GPIO10/D10/ SCK E5 GPIO13/D13/ RXD F5 GPIO19/A0 C6 GPIO9/D9/ nSSI D6 VCC E6 GPIO12/D12/ TXD F6 GPIO15/D15/ CTS/nSSI G6 GND H6 GPIO20/A1 G1 AVCC H1 GND G2 XTALOUT G3 XTALIN H3 GPIO31/SCL G5 GPIO21/nCS/ nRESET H5 GPIO22/nWR H2 VCC Pin Descriptions Table 38.Pin Descriptions Pin H3 F3 F4 Name GPIO31/SCK GPIO30/SDA GPIO29/OTGID Type IO IO IO Description GPIO31: General Purpose IO SCK: I2C EEPROM SCK GPIO30: General Purpose IO SDA: I2C EEPROM SDA GPIO29: General Purpose IO OTGID: Input for OTG ID pin. When used as OTGID, this pin must be tied high through an external pull-up resistor. Assuming VCC = 3.0V, a 10K to 40K resistor must be used. GPIO24: General Purpose IO INT: HPI INT IRQ0: Interrupt Request 0. See Register 0xC006. This pin is also one of two possible GPIO wakeup sources. GPIO23: General Purpose IO nRD: HPI nRD GPIO22: General Purpose IO nWR: HPI nWR GPIO21: General Purpose IO nCS: HPI nCS H4 GPIO24/INT/IRQ0 IO G4 H5 G5 GPIO23/nRD GPIO22/nWR GPIO21/nCS IO IO IO Document #: 38-08014 Rev. *G Page 63 of 78 [+] Feedback CY7C67200 Table 38.Pin Descriptions (continued) Pin H6 F5 F6 Name GPIO20/A1 GPIO19/A0 GPIO15/D15/CTS/ nSSI Type IO IO IO Description GPIO20: General Purpose IO A1: HPI A1 GPIO19: General Purpose IO A0: HPI A0 GPIO15: General Purpose IO D15: D15 for HPI CTS: HSS CTS nSSI: SPI nSSI GPIO14: General Purpose IO D14: D14 for HPI RTS: HSS RTS GPIO13: General Purpose IO D13: D13 for HPI RXD: HSS RXD (Data is received on this pin) GPIO12: General Purpose IO D12: D12 for HPI TXD: HSS TXD (Data is transmitted from this pin) GPIO11: General Purpose IO D11: D11 for HPI MOSI: SPI MOSI GPIO10: General Purpose IO D10: D10 for HPI SCK: SPI SCK GPIO9: General Purpose IO D9: D9 for HPI nSSI: SPI nSSI GPIO8: General Purpose IO D8: D8 for HPI MISO: SPI MISO GPIO7: General Purpose IO D7: D7 for HPI TX: UART TX (Data is transmitted from this pin) GPIO6: General Purpose IO D6: D6 for HPI RX: UART RX (Data is received on this pin) GPIO5: General Purpose IO D5: D5 for HPI GPIO4: General Purpose IO D4: D4 for HPI GPIO3: General Purpose IO D3: D3 for HPI GPIO2: General Purpose IO D2: D2 for HPI GPIO1: General Purpose IO D1: D1 for HPI GPIO0: General Purpose IO D0: D0 for HPI USB Port 1A D- USB Port 1A D+ USB Port 2A D- USB Port 2A D+ Crystal Input or Direct Clock Input Crystal output. Leave floating if direct clock source is used. Reset Page 64 of 78 E4 GPIO14/D14/RTS IO E5 GPIO13/D13/RXD IO E6 GPIO12/D12/TXD IO D4 GPIO11/D11/MOSI IO D5 GPIO10/D10/SCK IO C6 GPIO9/D9/nSSI IO C5 GPIO8/D8/MISO IO B5 GPIO7/D7/TX IO B4 GPIO6/D6/RX IO C4 B3 A3 C3 A2 B2 F2 E3 C2 D3 G3 G2 A5 GPIO5/D5 GPIO4/D4 GPIO3/D3 GPIO2/D2 GPIO1/D1 GPIO0/D0 DM1A DP1A DM2A DP2A XTALIN XTALOUT nRESET IO IO IO IO IO IO IO IO IO IO Input Output Input Document #: 38-08014 Rev. *G [+] Feedback CY7C67200 Table 38.Pin Descriptions (continued) Pin A6 F1 E2 E1 C1 D1 D2 G1 B1 H2, D6, A4 G6, B6, A1, H1 Name Reserved BOOSTVCC VSWITCH BOOSTGND OTGVBUS CSWITCHA CSWITCHB AVCC AGND VCC GND Type - Power Analog Output Ground Analog IO Analog Analog Power Ground Power Ground Description Tie to Gnd for normal operation. Booster Power Input: 2.7V to 3.6V Booster Switching Output Booster Ground USB OTG Vbus Charge Pump Capacitor Charge Pump Capacitor USB Power USB Ground Main VCC Main Ground Absolute Maximum Ratings This section lists the absolute maximum ratings. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. Storage Temperature ............................................................................................................................................-40C to +125C Ambient Temperature with Power Supplied ............................................................................................................-40C to +85C Supply Voltage to Ground Potential ...........................................................................................................................0.0V to +3.6V DC Input Voltage to Any General Purpose Input Pin .............................................................................................................. 5.5V DC Voltage Applied to XTALIN....................................................................................................................... -0.5V to VCC + 0.5V Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................................................................................. > 2000V Max Output Current, per Input Output. .................................................................................................................................. 4 mA Operating Conditions TA (Ambient Temperature Under Bias)....................................................................................................................-40C to +85C Supply Voltage (VCC, AVCC) ....................................................................................................................................+3.0V to +3.6V Supply Voltage (BoostVCC)[5] ...................................................................................................................................+2.7V to +3.6V Ground Voltage ........................................................................................................................................................................... 0V FOSC (Oscillator or Crystal Frequency) ............................................................................................................. 12 MHz 500 ppm ............................................................................................................................................................................ Parallel Resonant Crystal Requirements (XTALIN, XTALOUT) Table 39.Crystal Requirements Crystal Requirements, (XTALIN, XTALOUT) Parallel Resonant Frequency Frequency Stability Load Capacitance Driver Level Start-up Time Mode of Vibration: Fundamental -500 20 Min. Typical 12 +500 33 500 5 Max. Unit MHz PPM pF W ms Note 5. The on-chip voltage booster circuit boosts BoostVCC to provide a nominal 3.3V VCC supply. Document #: 38-08014 Rev. *G Page 65 of 78 [+] Feedback CY7C67200 DC Characteristics Table 40.DC Characteristics[6] Parameter VCC, AVCC BoosVCC VIH VIL II VOH VOL IOH IOL CIN VHYS ICC[7, 8] ICCB[7, 8] ISLEEP Description Supply Voltage Supply Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Voltage HIGH Output LOW Voltage Output Current HIGH Output Current LOW Input Pin Capacitance Hysteresis on nReset Pin Supply Current Sleep Current 2 transceivers powered USB Peripheral: includes 1.5K internal pull up Without 1.5K internal pull up ISLEEPB Sleep Current with Booster Enabled USB Peripheral: includes 1.5K internal pull up Without 1.5K internal pull up Supply Current with Booster Enabled 2 transceivers powered Except D+/D- D+/D- 250 80 135 210 5 210 5 100 180 500 30 500 30 0< VIN < VCC IOUT = 4 mA IOUT = -4 mA -10.0 2.4 0.4 4 4 10 15 Conditions Min. 3.0 2.7 2.0 Typ. 3.3 Max. 3.6 3.6 5.5 0.8 +10.0 Unit V V V V A V V mA mA pF pF mV mA mA A A A A Table 41.DC Characteristics: Charge Pump Parameter VA_VBUS_OUT TA_VBUS_RISE IA_VBUS_OUT CDRD_VBUS VA_VBUS_LKG VDRD_DATA_LKG ICHARGE ICHARGEB IB_DSCHG_IN VA_VBUS_VALID Description Regulated OTGVBUS Voltage VBUS Rise Time Maximum Load Current OUTVBUS Bypass Capacitance OTGVBUS Leakage Voltage Dataline Leakage Voltage Charge Pump Current Draw ILOAD = 8 mA ILOAD = 0 mA Charge Pump Current Draw with ILOAD = 8 mA Booster Active ILOAD = 0 mA B-Device (SRP Capable) Discharge Current A-Device VBUS Valid 0V< VBUS < 5.25V 4.4 20 0 30 0 4.4V< VBUS < 5.25V OTGVBUS not driven Conditions 8 mA< ILOAD < 10 mA ILOAD = 10 mA 8 1.0 Min. 4.4 Typ. Max. 5.25 100 10 6.5 200 342 20 1 45 5 8 Unit V ms mA pF mV mV mA mA mA mA mA V Notes 6. All tests were conducted with Charge pump off. 7. ICC and ICCB values are the same regardless of USB host or peripheral configuration. 8. There is no appreciable difference in ICC and ICCB values when only one transceiver is powered. Document #: 38-08014 Rev. *G Page 66 of 78 [+] Feedback CY7C67200 Table 41.DC Characteristics: Charge Pump (continued) Parameter VA_SESS_VALID VB_SESS_VALID VA_SESS_END E RPD RA_BUS_IN RB_SRP_UP RB_SRP_DWN USB Transceiver USB 2.0-compatible in full- and low-speed modes. This product was tested as compliant to the USB-IF specification under the test identification number (TID) of 100390449 and is listed on the USB-IF's integrators list. Description A-Device Session Valid B-Device Session Valid B-Device Session End Efficiency When Loaded Data Line Pull Down A-device VBUS Input Impedance to GND B-device VBUS SRP Pull Up B-device VBUS SRP Pull Down VBUS is not being driven Pull-up voltage = 3.0V ILOAD = 8 mA, VCC = 3.3V 14.25 40 281 656 Conditions Min. 0.8 0.8 0.2 75 24.8 100 Typ. Max. 2.0 4.0 0.8 Unit V V V % k AC Timing Characteristics Reset Timing tRESET nRESET tIOACT nRD or nWRL or nWRH Reset Timing Parameter tRESET tIOACT Description nRESET Pulse Width nRESET HIGH to nRD or nWRx Active Min. 16 200 Typ. Max. Unit clocks[9] s Note 9. Clock is 12 MHz nominal. Document #: 38-08014 Rev. *G Page 67 of 78 [+] Feedback CY7C67200 Clock Timing tCLK tLOW tHIGH tFALL tRISE XTALIN Clock Timing Parameter Description Min. Typ. Max. Unit fCLK vXINH[10] tCLK tHIGH tLOW tRISE tFALL Duty Cycle Clock Frequency Clock Input High (XTALOUT left floating) Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time 45 1.5 83.17 36 36 12.0 3.0 83.33 3.6 83.5 44 44 5.0 5.0 55 MHz V ns ns ns ns ns % I2C EEPROM Timing 1. I2C EEPROM Bus Timing - Serial I/O tLOW tHIGH tR tF SCL tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO tBUF SDA IN tAA tDH SDA OUT Parameter Description Min. Typical fSCL tLOW tHIGH tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH Clock Frequency Clock Pulse Width Low Clock Pulse Width High Clock Low to Data Out Valid Bus Idle Before New Transmission Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Input Rise Time Input Fall Time Stop Setup Time Data Out Hold Time Max. 400 1300 600 900 1300 600 600 0 100 300 300 600 0 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns Note 10. vXINH is required to be 3.0V to obtain an internal 50/50 duty cycle clock. Document #: 38-08014 Rev. *G Page 68 of 78 [+] Feedback CY7C67200 HPI (Host Port Interface) Write Cycle Timing tCYC tASU tWP tAH ADDR [1:0] tCSSU tCSH nCS nWR nRD Dout [15:0] tDSU tWDH Parameter Description Min. Typical Max. Unit tASU tAH tCSSU tCSH tDSU tWDH tWP tCYC Address Setup Address Hold Chip Select Setup Chip Select Hold Data Setup Write Data Hold Write Pulse Width Write Cycle Time -1 -1 -1 -1 6 2 2 6 ns ns ns ns ns ns T[11] T[11] Note 11. T = system clock period = 1/48 MHz. Document #: 38-08014 Rev. *G Page 69 of 78 [+] Feedback CY7C67200 HPI (Host Port Interface) Read Cycle Timing tCYC tASU tRP tAH ADDR [1:0] tCSSU tCSH nCS nWR tRDH nRD Din [15:0] tACC tRDH Parameter Description Min. Typ. Max. Unit tASU tAH tCSSU tCSH tACC tRDH tRP tCYC Address Setup Address Hold Chip Select Setup Chip Select Hold Data Access Time, from HPI_nRD falling Read Data Hold, relative to the earlier of HPI_nRD rising or HPI_nCS rising Read Pulse Width Read Cycle Time -1 -1 -1 -1 1 0 2 6 7 ns ns ns ns T[11] ns T[11] T[11] Document #: 38-08014 Rev. *G Page 70 of 78 [+] Feedback CY7C67200 HSS BYTE Mode Transmit qt_clk CPU_A[2:0] CPUHSS_cs CPU_wr TxRdy flag HSS_TxD start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit BT BT CPU may start another BYTE transmit right after TxRdy goes high Byte transmit triggered by a CPU write to the HSS_TxData register TxRdy low to start bit delay: 0 min, BT max when starting from IDEL. For back to back transmit, new START Bit begins immediately following previous STOP bit. (BT = bit period) start of last data bit to TxRdy high: 0 min, 4 T max. (T is qt_clk period) programmable 1 or 2 stop bits. 1 stop bit shown. qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU operations and HSS port operations. Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value `1'. BT = bit time = 1/baud rate. HSS Block Mode Transmit BT HSS_TxD t GAP BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value. The BLOCK mode STOP bit time, tGAP = (HSS_GAP - 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS Transmit Gap register 90xC074]. The default tGAP is 2 BT. BT = bit time = 1/baud rate. HSS BYTE and BLOCK Mode Receive BT +/- 5% BT +/- 5% received byte added to receive FIFO during the final data bit time HSS_RxD start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit 10 BT +/- 5% Receive data arrives asynchronously relative to the internal clock. Incoming data bit rate may deviate from the programmed baud rate clock by as much as 5% (with HSS_RATE value of 23 or higher). BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag. BLOCK mode received bytes are written directly to the memory system. Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value `1'. BT = bit time = 1/baud rate. Document #: 38-08014 Rev. *G Page 71 of 78 [+] Feedback CY7C67200 Hardware CTS/RTS Handshake tCTShold tCTSsetup HSS_RTS tCTSsetup tCTShold HSS_CTS HSS_TxD Start of transmission delayed until HSS_CTS goes high Start of transmission not delayed by HSS_CTS tCTSset-up: HSS_CTS setup time before HSS_RTS = 1.5T min. tCTShold: HSS_CTS hold time after START bit = 0 ns min. T = 1/48 MHz. When RTS/CTS hardware handshake is enabled, transmission can be held off by deasserting HSS_CTS at least 1.5T before HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit. HSS_RTS is deasserted in the third data bit time. An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit. Document #: 38-08014 Rev. *G Page 72 of 78 [+] Feedback CY7C67200 Register Summary Table 42. Register Summary R/W R R Address Register 0x0140 0x0142 HPI Breakpoint Interrupt Routing Bit 15 Bit 7 Address... ...Address VBUS to HPI Enable Resume2 to HPI Enable W R/W 1: 0x0144 SIEXmsg 2: 0x0148 0x02n0 Device n Endpoint n Control Data... ...Data Reserved IN/OUT Sequence Ignore Enable Select R/W R.W R/W 0x02n2 0x02n4 0x02n6 Device n Endpoint n Address Device n Endpoint n Count Device n Endpoint n Status Address... ...Address Reserved ...Count Reserved Stall Flag R/W R 0x02n8 0xC000 Device n Endpoint n Count Re- Result... sult ...Result CPU Flags Reserved... ...Reserved R/W R R/W 0xC002 0xC004 0xC006 Bank Hardware Revision GPIO Control Address... ...Address Revision... ...Revision Write Protect Enable HSS Enable R/W R/W 0xC008 0xC00A CPU Speed Power Control Reserved... .Reserved Reserved Host/Device 2 Reserved Wake Enable CPU Speed Host/Device 1 OTG Reserved Wake Enable Wake Enable GPI Reserved Wake Enable Timeout Flag Period Select OTG Interrupt Enable Out Mailbox Interrupt Enable Reserved SPI Interrupt Enable UART Interrupt Enable Boost 3V OK Lock Enable Reserved HSS Wake Enable Sleep Enable WDT Enable UD Reserved Reserved SPI Enable Reserved SAS Enable Mode Select Interrupt 0 Interrupt 0 Polarity Select Enable Reserved Global Interrupt Enable Negative Flag Overflow Flag Carry Flag Zero Flag NAK Flag Length Set-up Exception Flag Flag Overflow Flag Sequence Status Underflow Flag Timeout Flag Count... Stall Enable ISO Enable NAK Interrupt Direction Enable Select Enable ARM Enable ID to HPI Enable Resume1 to HPI Enable SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Swap 1 HPI Enable CPU Enable HPI Enable CPU Enable Enable Enable Reserved Done2 to HPI Done1 to HPI Reset1 to HPI HPI Swap 0 Enable Enable Enable Enable Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Default High Default Low 0000 0000 0000 0000 0001 0100 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx OUT IN xxxx xxxx Exception Flag Exception Flag Error Flag ACK Flag xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 000x xxxx 0000 0001 000x xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 000F SPI 0000 0000 Wake Enable Halt Enable Reset Strobe 0000 0000 0000 0000 0000 0000 HPI Reserved Wake Enable R/W 0xC00C Watchdog Timer Reserved... ...Reserved R/W 0xC00E Interrupt Enable Reserved Host/Device 2 Host/Device 1 0000 0000 Interrupt Interrupt Enable Enable Timer 1 Interrupt Enable Timer 0 Interrupt Enable 0001 0000 HSS Interrupt In Mailbox Enable Interrupt Enable R/W 0xC098 OTG Control Reserved D+ Pull-down Enable R/W R/W R/W R/W R R/W 0: 0xC010 Timer n 1: 0xC012 0xC014 Breakpoint Count... ...Count Address... ...Address 1: 0xC018 Extended Page n Map 2: 0xC01A 0xC01E 0xC020 0xC022 GPIO 0 Output Data GPIO 0 Input Data GPIO 0 Direction Address... ...Address GPIO15 GPIO7 GPIO15 GPIO7 GPIO15 GPIO7 GPIO14 GPIO6 GPIO14 GPIO6 GPIO14 GPIO6 D- Pull-down Enable GPIO Interrupt Enable VBUS Receive Pull-up Enable Disable Reserved D+ D- 0000 0000 Charge Pump VBUS Discharge Enable Pull-up Enable Pull-up Enable Enable OTG Data Sta- ID tus Status VBUS Valid Flag 0000 0XXX 1111 1111 1111 1111 0000 0000 0000 0000 GPIO13 GPIO5 GPIO13 GPIO5 GPIO13 GPIO5 GPIO12 GPIO4 GPIO12 GPIO4 GPIO12 GPIO4 GPIO11 GPIO3 GPIO11 GPIO3 GPIO11 GPIO3 GPIO10 GPIO2 GPIO10 GPIO2 GPIO10 GPIO2 GPIO9 GPIO1 GPIO9 GPIO1 GPIO9 GPIO1 GPIO8 GPIO0 GPIO8 GPIO0 GPIO8 GPIO0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Document #: 38-08014 Rev. *G Page 73 of 78 [+] Feedback CY7C67200 Table 42. Register Summary (continued) R/W R/W R R/W R/W Address Register 0xC024 0xC026 0xC028 0xC03C GPIO 1 Output Data GPIO 1 Input Data GPIO 1 Direction USB Diagnostic Bit 15 Bit 7 GPIO31 GPIO23 GPIO31 GPIO23 GPIO31 GPIO23 Reserved ...Reserved R/W 0xC070 HSS Control HSS Enable Bit 14 Bit 6 GPIO30 GPIO22 GPIO30 GPIO22 GPIO30 GPIO22 Bit 13 Bit 5 GPIO29 GPIO21 GPIO29 GPIO21 GPIO29 GPIO21 Bit 12 Bit 4 Reserved GPIO20 Reserved GPIO20 Reserved GPIO20 GPIO19 Reserved Port 1A Diag- Reserved... nostic Enable FS Pull-up Enable Reserved XOFF Enable Force Select CTS Enable GPIO19 Reserved GPIO24 GPIO19 Reserved GPIO24 Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 GPIO24 Default High Default Low 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Receive Inter- Done Interrupt 0000 0000 rupt Enable Enable 0000 0000 0000 0000 0001 0111 0000 0000 0000 1001 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 Counter... 0000 0000 0000 0000 0000 0000 0000 0000 Counter... 0000 0000 0000 0000 0000 0000 Sequence Select Sync Enable ISO Enable Reserved Arm Enable 0000 0000 0000 0000 0000 0000 Port Select Reserved Overflow Flag NAK Flag Length Reserved Exception Flag Sequence Status Underflow Flag Timeout Flag Count... Reserved Error Flag ACK Flag 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Endpoint Select 0000 0000 0000 0000 0000 0000 0000 0000 Address Port A D+ Status Reserved Port A D- Status Port A Force D State Reserved Reserved LOA Suspend Enable Mode Select Reserved Reserved Port A SOF/EOP Enable Reserved 0000 0000 xxxx 0000 0000 0000 Port 2A Diag- Reserved nostic Enable Pull-down Enable LS Pull-up Enable RTS CTS XOFF Polarity Select Polarity Select Transmit Ready HSS Baud... Transmit Done Receive Done One Interrupt Flag Interrupt Flag Stop Bit R/W R/W R/W R/W R/W R/W R/W R/W 0xC072 0xC074 0xC076 0xC078 0xC07A 0xC07C 0xC07E 0xC080 0xC0A0 0xC082 0xC0A2 0xC084 0xC0A4 0xC086 0xC0A6 HSS Baud Rate HSS Transmit Gap HSS Data HSS Receive Address HSS Receive Counter HSS Transmit Address HSS Transmit Counter Host n Control Reserved ...Baud Reserved Transmit Gap Select Reserved Data Address... ...Address Reserved ...Counter Address.. ...Address Reserved ...Counter Reserved Preamble Enable Host n Address Host n Count Host n PID Address... ...Address Reserved ...Count Reserved Stall Flag W R W R/W 0xC086 0xC0A4 0xC088 0xC0A8 0xC088 0xC0A8 0xC08A 0xC0AA Host n EP Status Host n Count Result Host n Device Address USB n Control Reserved PID Select Result... ...Result Reserved... ...Reserved Reserved Port A Resistors Enable R/W 0xC08C Host 1 Interrupt Enable VBUS Interrupt Enable Reserved Packet Receive Receive Pack- Receive Mode Select Overflow Flag et Ready Flag Ready Flag R/W R/W R ID Interrupt Enable SOF/EOP Interrupt Enable Port A Connect Change Interrupt Enable Reserved 0000 0000 Port A Reserved Wake Interrupt Enable ID Interrupt Enable EP6 Interrupt Enable Address Reserved Done Interrupt Enable SOF/EOP Interrupt Enable EP1 Interrupt Enable Reset Interrupt Enable EP0 Interrupt Enable 0000 0000 R/W 0xC08C Device 1 Interrupt Enable VBUS Interrupt Enable EP7 Interrupt Enable SOF/EOP Reserved Timeout Interrupt Enable EP4 Interrupt Enable EP3 Interrupt Enable EP2 Interrupt Enable 0000 0000 EP5 Interrupt Enable 0000 0000 R/W 0xC08E 0xC0AE Device n Address Reserved... ...Reserved 0000 0000 0000 0000 Document #: 38-08014 Rev. *G Page 74 of 78 [+] Feedback CY7C67200 Table 42. Register Summary (continued) R/W R/W Address Register 0xC090 Host 1 Status Bit 15 Bit 7 VBUS Interrupt Flag Reserved Bit 14 Bit 6 ID Interrupt Flag Bit 13 Bit 5 Reserved Bit 12 Bit 4 Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 SOF/EOP Interrupt Flag Port A ConReserved nect Change Interrupt Flag Port A SE0 Status Reserved Bit 8 Bit 0 Reserved Default High Default Low xxxx xxxx Port A Reserved Wake Interrupt Flag ID Interrupt Flag EP6 Interrupt Flag Reserved Done Interrupt Flag Reset Interrupt Flag EP0 Interrupt Flag xxxx xxxx R/W 0xC090 Device 1 Status VBUS Interrupt Flag EP7 Interrupt Flag SOF/EOP Interrupt Flag EP4 Interrupt Flag EP3 Interrupt Flag EP2 Interrupt Flag EP1 Interrupt Flag xxxx xxxx EP5 Interrupt Flag Count... xxxx xxxx R/W R 0xC092 0xC0B2 0xC092 0xC0B2 Host n SOF/EOP Count Device n Frame Number Reserved ...Count SOF/EOP Timeout Flag ...Frame Reserved ...Counter Reserved ...Count Reserved ...Frame Reserved SOF/EOP Timeout Interrupt Count 0010 1110 1110 0000 Reserved Frame... 0000 0000 0000 0000 Counter... Count... Frame... SOF/EOP Interrupt Enable Port A Reserved Wake Interrupt Enable Port A Connect Change Interrupt Enable Reserved Reserved 0000 0000 0000 0000 0000 0000 R W R R/W 0xC094 0xC0B4 0xC094 0xC0B4 0xC096 0xC0B6 0xC0AC Host n SOF/EOP Counter Device n SOF/EOP Count Host n Frame Host 2 Interrupt Enable Reserved Done Interrupt Enable SOF/EOP Interrupt Enable EP1 Interrupt Enable SOF/EOP Interrupt Flag Reset Interrupt Enable EP0 Interrupt Enable Reserved Done Interrupt Flag Reset Interrupt Flag 0000 0000 R/W 0xC0AC Device 2 Interrupt Enable Reserved SOF/EOP Wake Timeout Inter- Interrupt rupt Enable Enable EP6 Interrupt Enable EP5 Interrupt Enable EP4 Interrupt Enable EP3 Interrupt Enable EP2 Interrupt Enable 0000 0000 EP7 Interrupt Enable R/W 0xC0B0 Host 2 Status Reserved Reserved 0000 0000 xxxx xxxx xxxx xxxx Port A Reserved Wake Interrupt Flag Port A ConReserved nect Change Interrupt Flag SOF/EOP Timeout Interrupt Enable Port A SE0 Status Wake Interrupt Flag Reserved R/W 0xC0B0 Device 2 Status Reserved SOF/EOP Interrupt Flag xxxx xxxx EP7 EP6 EP5 EP4 EP3 EP2 EP1 Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag R/W R/W 0xC0C6 0xC0C8 HPI Mailbox SPI Configuration Message... ...Message 3Wire Enable Phase Select SCK Scale Select Polarity Select SS Enable Byte Mode SS Delay Select FullDuplex SS Manual Read Enable Transmit Ready EP0 xxxx xxxx Interrupt Flag 0000 0000 0000 0000 Reserved 1000 0000 0001 1111 Receive Data Ready 0000 0001 1000 0000 0000 0000 Master Master Active Enable Enable R/W 0xC0CA SPI Control SCK Strobe Transmit Empty R/W 0xC0CC SPI Interrupt Enable Reserved... ...Reserved FIFO Init Receive Full Transmit Bit Length Receive Bit Length Receive Interrupt Enable Reserved Transmit Interrupt Enable Transfer Interrupt Enable 0000 0000 R 0xC0CE SPI Status Reserved... FIFO Error Flag Transmit Receive Interrupt Flag Interrupt Flag 0000 0000 Transfer 0000 0000 Interrupt Flag 0000 0000 Transmit Transmit 0000 0000 Interrupt Clear Interrupt Clear CRC Enable CRC Clear Receive CRC One in CRC Zero in CRC Reserved... 0000 0000 0000 0000 1111 1111 1111 1111 W 0xC0D0 SPI Interrupt Clear Reserved... ...Reserved R/W R/W 0xC0D2 0xC0D4 SPI CRC Control SPI CRC Value CRC Mode ...Reserved CRC.. ...CRC Document #: 38-08014 Rev. *G Page 75 of 78 [+] Feedback CY7C67200 Table 42. Register Summary (continued) R/W R/W R/W R/W R/W R/W R/W Address Register 0xC0D6 0xC0D8 0xC0DA 0xC0DC 0xC0DE 0xC0E0 SPI Data Port t SPI Transmit Address SPI Transmit Count SPI Receive Address SPI Receive Count UART Control Bit 15 Bit 7 Reserved Data Address... ...Address Reserved ...Count Address... ...Address Reserved ...Count Reserved... ...Reserved R 0xC0E2 UART Status Reserved... ...Reserved R/W R 0xC0E4 UART Data HPI Status Port Reserved Data VBUS Flag Resume2 Flag ID Flag Resume1 Flag Reserved SIE2msg SOF/EOP2 Flag SIE1msg Reserved Done2 Flag SOF/EOP1 Flag Done1 Flag Reset2 Flag Reset1 Flag Mailbox In Flag Mailbox Out Flag Receive Full Transmit Full Scale Select Baud Select UART Enable Count... Count... Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Default High Default Low xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111 0000 0000 0000 0000 0000 0000 0000 0000 Document #: 38-08014 Rev. *G Page 76 of 78 [+] Feedback CY7C67200 Ordering Information Table 43.Ordering Information Ordering Code Package Type PB-Free Temperature Range CY7C67200-48BAXI CY7C67200-BAXIT CY3663 48FBGA 48FBGA, Tape and reel Development Kit X X -40 to 85C -40 to 85C Package Diagram 48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48 TOP VIEW BOTTOM VIEW PIN 1 CORNER O0.05 M C O0.25 M C A B O0.300.05(48X) PIN 1 CORNER (LASER MARK) 12 A B C 7.000.10 5.25 D E F G H 7.000.10 0.75 3 4 5 6 6 5 4 3 2 1 A B C D E 2.625 F G H A A 1.875 0.75 B 7.000.10 3.75 B 7.000.10 0.530.05 0.25 C 0.15(4X) 0.210.05 0.10 C 51-85096-*F SEATING PLANE 0.36 C 1.20 MAX. Purchase of I2CTM components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. EZ-OTG is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-08014 Rev. *G Page 77 of 78 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C67200 Document History Page Document Title: CY7C67200 EZ-OTGTM Programmable USB On-The-Go Host/Peripheral Controller Document Number: 38-08014 REV. ECN NO. Issue Date Orig. of Change Description of Change ** *A *B 111872 116988 124954 03/22/02 08/23/02 04/10/03 MUL MUL MUL New Data Sheet Preliminary Data Sheet Added Memory Map Section and Ordering Information Section Moved Functional Register Map Tables into Register section General Clean-up Changed from "Preliminary" to "Preliminary Confidential" Added Interface Description Section and Power Savings and Reset Section Added Char Data General Clean-up Removed DRAM, MDMA, and EPP Added "Programmable" to the title page Corrected font to enable correct symbol display Final Data Sheet Changed Memory Map Section Added USB OTG Logo General Clean-up Removed "power consumption" bullet from the Features bullet list. Corrected number GPIO[31:20] to read GPIO[31:30] in Section "Standalone Mode". Made sentence into a Note in Section "Reset Pin" and repeated the note in Section "Host Port Interface (HPI)". Corrected the Host/Device 1 Interrupt Enable (Bit 8) Information in Section "Interrupt Enable Register [0xC00E] [R/W]". Corrected data on Write Protect Enable (Bit 15) Section "GPIO Control Register [0xC006] [R/W]" to read "the GPIO Mode Select [15:8] bits are read only until a chip reset". Re-wrote the Register Description in Section "SIEXmsg Register [W]". Put document on 2-column template and corrected grammar. Put the figure captions at the top of the figures per new template specifications. Added Static Discharge Voltage information in Section "Absolute Maximum Ratings" Added compliance statement and TID in Section "USB Transceiver". *C 126211 05/23/03 MUL *D *E 127334 129394 05/29/03 10/07/03 KKV MUL *F 472875 See ECN ARI *G 567317 See ECN KKVTMP Added the lead free information on the Ordering Information Section. Implemented the new template with no numbers on the headings. Document #: 38-08014 Rev. *G Page 78 of 78 [+] Feedback |
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